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Explorer
187 次查看
注册日期: ‎05-04-2018

Ultrascal+ MPSoC 晶振PPM使用要求

请问下,Ultrascal+ MPSoC的PS端晶振的PPM有没有具体需求,我使用的20PPM,查寄存器PLL能够锁定。

20PPM的晶振会不会影响DDR的使用速率。

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Xilinx Employee
Xilinx Employee
176 次查看
注册日期: ‎08-26-2010

回复: Ultrascal+ MPSoC 晶振PPM使用要求

Hi @shiyangcool,

 

在ds925(v1.14)的table 36上有period jitter,最大值50ps的要求:

http://www.xilinx.com/support/documentation/data_sheets/ds925-zynq-ultrascale-plus.pdf

 

Thanks
Simon
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