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Explorer
Explorer
119 次查看
注册日期: ‎12-28-2018

如何对XAPP1081中SpiSerDes.vhd模块做修改?

你们好:

目前正在做远程更新功能,借鉴了XAPP1081,由于该example是支持SPIx1,而我们是用的SPIx4。

1:请问对SpiSerDes.vhd做哪些关键性修改使得支持SPIx4?

2:目前使用的器件KU060,该远程升级需要用到STARTUPE3原语,该原语与v6系列有较大变化,

V6:

STARTUPE2_inst : STARTUP_VIRTEX6
port map (
DINSPI => inSpiMiso,
CLK => '0',
GSR => '0',
GTS => '0',
KEYCLEARB => '1',
PACK => '1',
USRCCLKO => intSpiClk,
USRCCLKTS => '0',
USRDONEO => '1',
USRDONETS => '1'
);

KU060

STARTUPE3_inst (
.CFGCLK(), // 1-bit output: Configuration main clock output
.CFGMCLK(), // 1-bit output: Configuration internal oscillator clock output
.DI(inSpiMiso), // 4-bit output: Allow receiving on the D input pin
.DO(outSpiMosi), // 4-bit input: Allows control of the D pin output
.EOS(), // 1-bit output: Active-High output signal indicating the End Of Startup
.PREQ(), // 1-bit output: PROGRAM request to fabric output
.DTS(4'b0), // 4-bit input: Allows tristate of the D pin
.FCSBO(1'b1), // 1-bit input: Controls the FCS_B pin for flash access
.FCSBTS(1'b0), // 1-bit input: Tristate the FCS_B pin
.GSR(1'b0), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port)
.GTS(1'b0), // 1-bit input: Global 3-state input (GTS cannot be used for the port )
.KEYCLEARB(1'b1), // 1-bit input: 
.PACK(1'b1), // 1-bit input: PROGRAM acknowledge input
.USRCCLKO(intSpiClk), // 1-bit input: User CCLK input
.USRCCLKTS(1'b0), // 1-bit input: User CCLK 3-state enable input
.USRDONEO(1'b1), // 1-bit input: User DONE pin output control
.USRDONETS(1'b1) // 1-bit input: User DONE 3-state enable output
);

其中STARTUPE3_inst 中的DI我认为是updata.bit数据或者是读flash的寄存器经过SpiSerDes.vhd后送往flash的接口,DO是接收flash回读的寄存器值,送往SpiSerDes.vhd

我不知道自己认为是否正确,如果正确,那么这个SpiSerDes.vhd需要修改成x4?如何修改呢

FCSBO与FCSBTS我不知道有何作用。

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Xilinx Employee
Xilinx Employee
60 次查看
注册日期: ‎08-26-2010

回复: 如何对XAPP1081中SpiSerDes.vhd模块做修改?

Hi @llaill123 

看看这个AR的附件里有exmaple:

https://china.xilinx.com/support/answers/62376.html

 

Thanks
Simon
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