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Participant
Participant
655 次查看
注册日期: ‎02-01-2018

请教有关methodology中的警告

在ultrafast设计法中,根据report_failfast报告中常常有关TIMING-6和TIMING-7的REVIEW,然后从report_methodology中查看详细信息,结果如下。

TIMING-6

The clocks CLK_OUT1_1 and rgmii_rxc are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks CLK_OUT1_1] -to [get_clocks rgmii_rxc]

TIMING-7

The clocks CLK_OUT1_1 and rgmii_rxc are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks CLK_OUT1_1] -to [get_clocks rgmii_rxc]

不是很能理解导致这两条警告的原因,求教,谢谢~

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Xilinx Employee
Xilinx Employee
548 次查看
注册日期: ‎07-17-2008

回复: 请教有关methodology中的警告

请看一下UG906,第286页,附录A中对于这两个check的描述。

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug906-vivado-design-analysis.pdf

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