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mkchan
Contributor
Contributor
227 次查看
注册日期: ‎05-08-2018

BITSLICE_RX_TX has conflict between ODDRE1, IDELAYE3 routing failed issue

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Dear Sir

Customer try to implement the ODDRE1 component and the IDELAYE3 component into one BITSLICE_RX_TX.

But, we got the message about [Vivado 12-2285] BITSLICE_RX_TX has conflict between OSERDES/OUT_FF CLKDIV/C pin, IDELAY instance CLK pin, because the nets on those pins are not same.

mkchan_0-1618454862850.png

 

We had checked the ug571 selectio document.

The page. 172 shows the CLK of the IDELAYE3 must be the same CLK as the ISERDESE3 CLKDIV.

And the page.186 shows the CLK of the ODELAYE3 must be the same CLK as the OSERDESE3 CLKDIV or the ODDRE1 C port.

Our question:

Is the IDELAYE3 clock mush be the same with OSERDESE3 CLKDIV or the ODDRE1 C port too?

Our Vivado version is use 2019.2 and the device is Ultrascale KU040. 

Thanks for your help.

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kren
Moderator
Moderator
153 次查看
注册日期: ‎08-21-2007

Yes, as the CLKDIV of ISERDESE3 and OSERDESE3 should be same.

-----------------------------------------------------Please don't forget to give kudos or accept as solution if information provided is helpful.---------------------------------------------------------------------

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kren
Moderator
Moderator
154 次查看
注册日期: ‎08-21-2007

Yes, as the CLKDIV of ISERDESE3 and OSERDESE3 should be same.

-----------------------------------------------------Please don't forget to give kudos or accept as solution if information provided is helpful.---------------------------------------------------------------------

在原帖中查看解决方案

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