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Capricorn98
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430 次查看
注册日期: ‎03-20-2021

ibert Ultrascale GTH

I want to use the IP of ibert Ultrascale GTH to analyze the correct of PHY between FPGA and AD9172,when I put the IP into my project, I get the problem of creating a successful link between them. At first, I thought it may be the PCB had some mistakes so i try to find some errors but there is no mistake. And Then i create the clock that the IP "ibert Ultrascale GTH" needs and create a new project which just includes the IP to take the test. The result is that i can create the near PCS link. What's the problem? I need your help!

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shengjie
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注册日期: ‎07-01-2019

Hi @Capricorn98 ,

 

You need to make sure the reference clock meets the spec and toggles at the correct speed. And please use example design of IBERT IP and add logics on the top level. Some customers just add it into project and it doesn't work normally sometimes.

Then use near-end PCS/PMA loopback to test the internal link.

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zhiq
Xilinx Employee
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注册日期: ‎06-02-2017

@Capricorn98 Hi,

Could you describe your question more clear. Per you said, you checked the PCB and no mistakes. And you can pass the Near end loopback test. So what's your question, do you want to get debug method?

I think you mean there's no connection error, but you need to check the SI of the link.

So you can create IBERT and try to check the entire link, if AD9172 has the function such as sending out some patterns, ensure the FPGA can check the link quality?

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Capricorn98
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注册日期: ‎03-20-2021

Thank you for your response. My problem is that when I put the ip “Ibert ultrascale gth” into my former project, I cannot create the near PCS link. Just as I said, if depart the two project, create an example project for ip “ibert ultrascale gth”, the near PCS link can be created. what’s the problem? Thanks for your reply!
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shengjie
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注册日期: ‎07-01-2019

Hi @Capricorn98 ,

 

Refer to pg173, the recommended and supported flow is to use the example design as-is, without modifications outsides the Vivado IDE.

There is no guarantee for correct behavior or measurements once the IBERT example design has been modified. Standard IBERT (not In-System) was designed to be used as a standalone bitstream out of the box without any modifications.

Just as I said in the last post, our customers have met strange behaviors when adding IBERT directly into project.  If you have difficulties on system clock routing, please add logics based on example design. Maybe you will create the near PCS link.

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Capricorn98
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注册日期: ‎03-20-2021

Thanks for your apply. And how can I check the AD9172's PHY PRBS Testing that uses PRBS pattern by the ip?

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shengjie
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231 次查看
注册日期: ‎07-01-2019

On the AD9172 side, please refer to datasheet:

https://www.analog.com/media/en/technical-documentation/data-sheets/AD9172.pdf

With PRBS feature available in ADC, the test is similar to link between two FPGAs. Enable PRBS pattern in ADC and use the same PRBS setting in IBERT.

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如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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