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Explorer
Explorer
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Registered: ‎01-18-2011

Сlock pattern when using TX_BITSLICE

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Hello

 

XAPP 1274, page 13: " A transmitter, TX_BITSLICE, can be used as a clock generator when the TX_BITSLICE.D[7:0] inputs
are tied to a regular pattern. The pattern
01010101 generates a clock of 625 MHz when the applied PLL_CLK is 1250 MHz. This setup generates perfectly synchronized clock/data interfaces. With the TX_BITSLICE attribute OUTPUT_PHASE_90, it is possible to automatically generate a clock that is phase shifted to the accompanying data by 90° or a quarter of its period.

 

TIP: The correct clock pattern 01010101 (not 10101010) [!?] must be applied to avoid any unnecessary bitslips on the receiver side."

 

I don't understand this TIP. Can someone explain to me why 10101010 is incorrect pattern?

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Community Manager
Community Manager
1,147 Views
Registered: ‎08-08-2007

hi @taganrog,

 

At the RX the stream of 01 will give a rising edge for the data to be captured on, 10 will give a falling edge. I suppose it would depend on how RX device behaves if you can tell it to start the word on a falling edge.

 

Sandy 

Thanks,
Sandy

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Highlighted
Community Manager
Community Manager
1,148 Views
Registered: ‎08-08-2007

hi @taganrog,

 

At the RX the stream of 01 will give a rising edge for the data to be captured on, 10 will give a falling edge. I suppose it would depend on how RX device behaves if you can tell it to start the word on a falling edge.

 

Sandy 

Thanks,
Sandy

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