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ymulder
Observer
Observer
2,751 Views
Registered: ‎02-27-2017

18K BRAM configurations available in UltraScale+

Hi community,

 

I would like to have 8 SDP BRAMs of 256x8 bytes. However, when I instantiate these using the SDP template, the device window after implementation shows that 8 36K BRAMs are inferred.

 

How is a 36K BRAM split into two 18K BRAMs? Is the minimum amount of entries for an 18K BRAM still 512?

 

If this is the limitation, how would you suggest to solve this problem?

 

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3 Replies
ymulder
Observer
Observer
2,745 Views
Registered: ‎02-27-2017

Sorry for my ignorance, I checked the memory resources guide again and found the answer. The minimum amount of entries is 512x36b when used as a SDP memory.

 

Memory resource guide

 

However, my question still remains, how would I implement 8 256x64b BRAMs instead? 

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ralfk
Xilinx Employee
Xilinx Employee
2,730 Views
Registered: ‎10-11-2007

Two x18 in parallel or one x36 in SDP. Either way, you won't be fully utilizing the blocks.

ymulder
Observer
Observer
2,728 Views
Registered: ‎02-27-2017

@ralfk That is what I was afraid of. I ran a test with using distributed RAM instead but that results in an explosion of resource utilization (as expected).

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