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mufeed029
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Registered: ‎06-20-2019

AC Timing Parameters of clock input to GC pins of XCZU28DR

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Hi Team,

I am using XCZU28DR RFSoC, and planing to give differential clock input of 156.25MHz to GC pins of bank 65. Can anyone help me to find out the ac parameters ( phase noise, jitter, etc.) of this input reference clocks.

 

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pthakare
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Registered: ‎08-08-2017

Hi @mufeed029 

There are no explicit specifications for Global clock inputs,  four GC pin pairs in each bank  have direct access to the global clock buffers, MMCMs, and PLLs that are in the CMT adjacent to the same I/O bank. 

The global clock buffer dont have any requirement on input clock jitter , it wil pass the same clock to output plus some additional jitter if internal supply powering these buffers are noisy.

MMCM and PLL have restriction on Maximum input clock jitter , it should be  < 20% of clock input period or 1 ns Max , othewise MMCM will not lock.

The Global clock buffers, MMCM and PLL switching characteristics are given in same datsheet.

 

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pthakare
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Registered: ‎08-08-2017

Hi @mufeed029 

Please refer to "RF Converters Clocking Characteristics"  in datasheet page 102.

https://www.xilinx.com/support/documentation/data_sheets/ds926-zynq-ultrascale-plus-rfsoc.pdf

 

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mufeed029
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Registered: ‎06-20-2019

Hi @pthakare 

Thanks for your reply.

The page number 102 in ds926 describing input clock specification of ADC and DAC sections.

I need input clock specifications of GC pins.

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pthakare
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Registered: ‎08-08-2017

Hi @mufeed029 

There are no explicit specifications for Global clock inputs,  four GC pin pairs in each bank  have direct access to the global clock buffers, MMCMs, and PLLs that are in the CMT adjacent to the same I/O bank. 

The global clock buffer dont have any requirement on input clock jitter , it wil pass the same clock to output plus some additional jitter if internal supply powering these buffers are noisy.

MMCM and PLL have restriction on Maximum input clock jitter , it should be  < 20% of clock input period or 1 ns Max , othewise MMCM will not lock.

The Global clock buffers, MMCM and PLL switching characteristics are given in same datsheet.

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post

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