08-10-2020 08:45 AM
Following The PG269 show us the Automatic Gain Control (ACG) can be implemented by using RF-ADC
How to step by step configure the IP and implement the AGC algorithm using RFSoC?
Looking for the reference examples of this kind of application but can not.
Thank you very much
08-10-2020 09:35 PM
There is readily available solution on AGC.
Customer need to implement their own AGC algorithm based on flags received from data converters.
08-11-2020 12:42 AM
Thank @pthakare for your quickly reply,
As I understand, AGC algorithm based on flags received from data converters, It means I will develop my algorithm based on RFDC Driver API Command? In the document PG269, we have several ways to implement AGC by using Digital Gain Compensation; Compensation Using QMC; Compensation Using PL Gain or Determining Gain-Change Latency. So we might do these things in VIVADO and RFDC Driver API? The information in the documentation is general, so I would looking for a typical example or a reference design where I know how can I start with.
Again, thank you very much for your considering.
08-20-2020 06:05 AM - edited 08-20-2020 06:05 AM
Use the API to set the two thresholds shown in your diagram.
You have to implement logic in your FPGA fabric to use the information provided by the thresholds you set to make attack / decay decisions, modifying the gain (VGA) through some IP that you create.
The solution in figure 89 shows you how Xilinx provides signals that assist the designer in providing an AGC solution, but is not a self-contained solution from Xilinx. Per the text around figure 89, one of the components, "AGC Algorithm / Decision logic", is yours to design.
The design is highly signal dependent. For instance, if you have a TDD (most bands in 5G) vs FDD (most bands in 3G) signal, your algorithm will vary considerably (attack, decay, integration time) so there's no general solution.
Have fun exploring this, read up on AGC - you'll grow considerably from this.
08-24-2020 12:57 AM
Hi Jerry @olupj
Thank you very much for your useful information.
I would like to know how we can set the two thresholds without the implementation logic in the FPGA fabric. I mean the first step should be implemented the design on the Vivado with the IPs. Based on this design, in the second step, we will use the API to set the thresholds and write a program for a given algorithm (Linear or Exponential function etc..)
Another question is the solution in figure 89, It shows that Xilinx just only use one block Data Converter in this design. Is there another block IP for this kind of application?
08-25-2020 07:59 AM
" Is there another block IP for this kind of application?"
I'll assume you're talking about the "AGC Algorithm" block and try to help under this assumption.
I believe the answer is no (free Xilinx IP), but didn't check. However it's not too hard to design.
Accumulate I^2 + Q^2 over some number of samples and compare that accumulated value to your desired range (integration time, number of samples). Then multiply (and rescale) your data as needed based on whether your in range, over range, or under range. Those measures will drive your attack and decay values (usually some fraction of your current value).
That's of course a simpler explanation, there is, however, ample information on the web to design this. For instance, here's something from Nutaq expanding on what I very briefly describe above.
One other small point from the diagram is that the processor is not used for real time control of AGC. It can set your integration time, attack, decay values and default gain (the AGC Algorithm interface). Then the processor is used as previously discussed to work with RFDC API.