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Adventurer
Adventurer
281 Views
Registered: ‎08-21-2017

Bug in IDELAYE3 simualtion model

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Hi all,

I found a problem in IDELAYE3 VHDL simulation model (2018.1 and 2018.3). When using TIME delay format, number of taps is calculated by dividing specified time with 5 ps.

function Idelaye3_InitDelayCount(
DelayFormat : in string;
DelayValue : in integer
) return integer is

begin
if(DelayFormat = "TIME") then
return integer(real(DelayValue)/5.0);
else return integer(DelayValue);
end if;
end;

The problem is in fact that Ultrascale+ architecture specifies average delay per tap to 4 ps:

elsif ((SIM_DEVICE = "ULTRASCALE_PLUS") or (SIM_DEVICE = "ULTRASCALE_PLUS_ES1") or (SIM_DEVICE = "ULTRASCALE_PLUS_ES2")) then
PER_BIT_FINE_DELAY <= 4;
PER_BIT_MEDIUM_DELAY <= 32;
INTRINSIC_FINE_DELAY <= 60 ps;
INTRINSIC_MEDIUM_DELAY <= 32 ps;
IDATAIN_INTRINSIC_DELAY <= 15 ps;
DATAIN_INTRINSIC_DELAY <= 32 ps;
CASC_IN_INTRINSIC_DELAY <= 32 ps;
CASC_RET_INTRINSIC_DELAY <= 32 ps;
DATA_OUT_INTRINSIC_DELAY <= 20 ps;
CASC_OUT_INTRINSIC_DELAY <= 45 ps;
end if;

This causes the actual configurable delay to be 80% of the required one.

Best regards

Srdjan

1 Solution

Accepted Solutions
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Community Manager
Community Manager
227 Views
Registered: ‎08-08-2007

Re: Bug in IDELAYE3 simualtion model

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Hi @srdjan.opacic 

 

Thank you for including such good detail in the post. I have filed a Change Request against the simulation Model. 

 

Regards,

Sandy

Thanks,
Sandy

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1 Reply
Highlighted
Community Manager
Community Manager
228 Views
Registered: ‎08-08-2007

Re: Bug in IDELAYE3 simualtion model

Jump to solution

Hi @srdjan.opacic 

 

Thank you for including such good detail in the post. I have filed a Change Request against the simulation Model. 

 

Regards,

Sandy

Thanks,
Sandy

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post