12-09-2015 05:49 AM
I am working in a project that shares some common features with the PONs (Upstream transmission) and i am trying to find out if an Ultrascale device with a BCDR Quick-Lock circuit is suitable (currently using 7-series FPGAs).
Like in PON's upstream transmission an FPGA (receiver) receives burst packets (200us each) followed by "silence time". Two consecutive packets may originate from different FPGAs (transmitters) each time and may have followed different "optical paths". The "locking times" of the 7-series FPGAs are comparable with the packet size, so i am trying to understand if BCDR Quick-Lock circuit can be used succesfully.
Because we don't have an Ultrascale board in our lab for testing i want to make the following questions:
a) Is there any additional docmentation except XAPP1252 (XAPP1252 Burst-Mode Clock Data Recovery with GTH and GTY Transceivers)?
b) How do i choose Threshold, WaitTime and stepSize inputs?
c) Regarding sop, I understand that i have to create a component that searches the incoming data (gt0_rxdata) and when it recognizes the preamble it asserts '1' in the sop input. Is that right?
d) In XAPP1252 i can see that RXCDR_CFG2 must be equal with PON's preamble. Why is this happening? Is there a problem to use a preamble different than PON's (different size and bits)?
Thanks in advance,
12-30-2015 10:50 PM