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Explorer
Explorer
284 Views
Registered: ‎04-11-2016

CLOCK SKEW OSERDESE3

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Hi,

I used 400 MHz high speed clock and generated 100 MHz CLKDIV of OSERDESE3 using BUFGCE_DIV but still I have the clock skew problem. See attachment.

Is there any solution for this?

CLOCK_DELAY_GROUP  and USER_CLOCK_ROOT have also no impact.

 

set_property CLOCK_DELAY_GROUP SERDES_X2Y2 [get_nets of [get_pins clkout3_buf/O]]
set_property CLOCK_DELAY_GROUP SERDES_X2Y2 [get_nets of [get_pins BUFGCE_DIV_inst/O]]

set_property USER_CLOCK_ROOT X2Y3 [get_nets of [get_pins clkout3_buf/O]]
set_property USER_CLOCK_ROOT X2Y3 [get_nets of [get_pins BUFGCE_DIV_inst/O]]

 

oserdes_skew.JPG
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1 Solution

Accepted Solutions
Explorer
Explorer
148 Views
Registered: ‎04-11-2016

Re: CLOCK SKEW OSERDESE3

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@hemangd
I got rid of clock skew using CLOCK_DELAY_GROUP but the design doesn't work as expected (working some time but not always). can it be that it overconstrained? 

The design woks in VCS (simulation).

Design:

I need to transfer data between A and B    i.e.   A <----> B.

A Side: 4 pins 2 TX and 2 RX

B side : also 4 pins 2 TX and 2 RX

clk is 400 MHz and clkdiv is 100 MHz for SERDES genearted from MMCM.

or  IO constraints make problem?

on O port I set the property like :

set_property PACKAGE_PIN A13 [get_ports {pin_o[0]}]

set_property IOSTANDARD LVCMOS18 [get_ports {pin_o[0]}]

set_property SLEW FAST [get_ports {pin_o[0]}]

on I port I set property like:

set_property PACKAGE_PIN C12 [get_ports {pin_i[0]}]

set_property IOSTANDARD LVCMOS18 [get_ports {pin_i[0]}]

and for timing set  set false paths for IO port like:

set_false_path -from [get_ports {pin_i[0]}]
set_false_path -to [get_ports {pin_o[0]}]

DO I also need to add IO delay or something like that?

 

 

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6 Replies
Moderator
Moderator
236 Views
Registered: ‎03-16-2017

Re: CLOCK SKEW OSERDESE3

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Hi @fpgalearner,

Check this AR. And make sure you are using optimal clocking topology for OSERDESE3. (report_methodology can help you here.)

https://www.xilinx.com/support/answers/67885.html

(Use BUFGCE for connection from MMCM CLKOUT0 to CLK pin of OSERDESE3 )

And also make sure that the clock is getting generated from MMCM. 

 

 

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
Explorer
Explorer
190 Views
Registered: ‎04-11-2016

Re: CLOCK SKEW OSERDESE3

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@hemangd

by applying clock delay group
set_property CLOCK_DELAY_GROUP SERDES_X2Y2 [get_nets of [get_pins clkout3_buf/O]]
set_property CLOCK_DELAY_GROUP SERDES_X2Y2 [get_nets of [get_pins BUFGCE_DIV_inst/O]]
I ended with

CRITICAL WARNING: [Common 17-165] Too many positional options when parsing 'clkout3_buf/O', please type 'get_nets -help' for usage info. /config/timing.xdc:92]
CRITICAL WARNING: [Common 17-165] Too many positional options when parsing 'BUFGCE_DIV_inst/O', please type 'get_nets -help' for usage info. [/config/timing.xdc:93]

what is wrong?

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Moderator
Moderator
178 Views
Registered: ‎03-16-2017

Re: CLOCK SKEW OSERDESE3

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@fpgalearner 

Check this AR https://www.xilinx.com/support/answers/46668.html

The "Too many positional args" errors in Tcl scripts are usually caused by copy / paste errors introducing unwanted (double-byte) characters into the text of the script file. We've also seen problems where we are not handling spaces in paths correctly.

 

Did you go through my last thread regarding clocking topology?

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Explorer
Explorer
149 Views
Registered: ‎04-11-2016

Re: CLOCK SKEW OSERDESE3

Jump to solution

@hemangd
I got rid of clock skew using CLOCK_DELAY_GROUP but the design doesn't work as expected (working some time but not always). can it be that it overconstrained? 

The design woks in VCS (simulation).

Design:

I need to transfer data between A and B    i.e.   A <----> B.

A Side: 4 pins 2 TX and 2 RX

B side : also 4 pins 2 TX and 2 RX

clk is 400 MHz and clkdiv is 100 MHz for SERDES genearted from MMCM.

or  IO constraints make problem?

on O port I set the property like :

set_property PACKAGE_PIN A13 [get_ports {pin_o[0]}]

set_property IOSTANDARD LVCMOS18 [get_ports {pin_o[0]}]

set_property SLEW FAST [get_ports {pin_o[0]}]

on I port I set property like:

set_property PACKAGE_PIN C12 [get_ports {pin_i[0]}]

set_property IOSTANDARD LVCMOS18 [get_ports {pin_i[0]}]

and for timing set  set false paths for IO port like:

set_false_path -from [get_ports {pin_i[0]}]
set_false_path -to [get_ports {pin_o[0]}]

DO I also need to add IO delay or something like that?

 

 

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Moderator
Moderator
132 Views
Registered: ‎03-16-2017

Re: CLOCK SKEW OSERDESE3

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Hi @fpgalearner

Since your clock skew has been resolved, kindly close this thread by marking it as accepted solution and create a new topic with your new issues so community can help you better. 

 

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Historian
Historian
68 Views
Registered: ‎01-23-2009

Re: CLOCK SKEW OSERDESE3

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Just to fill in an earlier part of the question. The "Too many positional arguments" error was due to a typo. Your command used

get_nets of [get_pins clkout3_buf/O]

You missed the dash in front of -of; so it should have been

get_nets -of [get_pins clkout3_buf/O]

With the dash, -of is not a "positional" argument, so you have only one positional argument (the get_pins command). But without the dash, there are two positional arguments; the word "of" and the get_pins command.

Avrum