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Visitor
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Registered: ‎04-04-2019

CMT: How to compare with Intel PLLs

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Dear Forum,

 

I want to implement a design on a Xilinx-FPGA which is currently running on an Intel-FPGA.

My design uses 5 of the 12 available "General purpose PLLs" and 9 of the 16 available "Global Clock Networks".

I prefer to use the ZU2CG-SoC for the implementation but this one has "only" 3 CMTs.

How to compare the CMTs from Xilinx with the PLLs from Intel?

 

Thanks in advance!

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Moderator
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Registered: ‎04-18-2011

Re: CMT: How to compare with Intel PLLs

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Yes

1 MMCM and 2 x PLL

The MMCM is considered for clocking the fabric. It provides frequency synthesis, deskewing, phase shifting and spread spectrum clocking capability. 

The PLL is less flexibile and is intended for generating clocking for the IO. It has some subset of the MMCM flexibility. 

A proper understanding of the clocking structure can be gleaned from this user guide. I would proceed by getting familiar with this guide. 

Since you are moving to Xilinx it would make sense to understand the ultrafast design methodology also. 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug949-vivado-design-methodology.pdf

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug1231-ultrafast-design-methodology-quick-reference.pdf

Also this document could be good, it covers migration from other xilinx device families but might be useful to you.

https://www.xilinx.com/support/documentation/sw_manuals/ug1026-ultrascale-migration-guide.pdf

Keith

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Registered: ‎04-18-2011

Re: CMT: How to compare with Intel PLLs

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First port of call should be here. 

https://www.xilinx.com/support/documentation/user_guides/ug572-ultrascale-clocking.pdf

It can explain the clocking structure in ultrascale and also give you an idea of the capability of the MMCM and PLL in the CMT.

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Registered: ‎04-04-2019

Re: CMT: How to compare with Intel PLLs

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Thx!

I haven't read the documentation deeply, but I understood that one CMT has 2 PLLs.

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Moderator
Moderator
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Registered: ‎04-18-2011

Re: CMT: How to compare with Intel PLLs

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Yes

1 MMCM and 2 x PLL

The MMCM is considered for clocking the fabric. It provides frequency synthesis, deskewing, phase shifting and spread spectrum clocking capability. 

The PLL is less flexibile and is intended for generating clocking for the IO. It has some subset of the MMCM flexibility. 

A proper understanding of the clocking structure can be gleaned from this user guide. I would proceed by getting familiar with this guide. 

Since you are moving to Xilinx it would make sense to understand the ultrafast design methodology also. 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug949-vivado-design-methodology.pdf

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug1231-ultrafast-design-methodology-quick-reference.pdf

Also this document could be good, it covers migration from other xilinx device families but might be useful to you.

https://www.xilinx.com/support/documentation/sw_manuals/ug1026-ultrascale-migration-guide.pdf

Keith

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