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f.gavioli
Visitor
Visitor
497 Views
Registered: ‎07-17-2019

Calculate duty cycle of an input PWM signal

Hi,
I would like to implement a PWM signal reader in FPGA PL.
Specifically, the signal comes out via a pin from a RC receiver, and gets connected to an ultra96 board via the low speed gpio header.
I am working with a 100Hz signal with a variable duty cycle from 10% to 20%.
Problem is, i would like to read the signal and calculate the duty cycle from the PL, and then pass it to the PS via AXI.

Is there any ready-to-use IP to achieve this? If the answer is no, could anyone point me to the right direction to implement it in HLS?

Thanks,
Federico

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bruce_karaffa
Scholar
Scholar
481 Views
Registered: ‎06-21-2017

You need to make a couple counters.  One to count a 10 mS period (1/100Hz), one to count up when the incoming signal is high.  The value of the second counter is your duty cycle if you put the decimal place in the right spot.

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