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alen89
Participant
Participant
809 Views
Registered: ‎06-26-2019

Camera link implementation

Dear,

I am working with camera link in Zynq ultrascale+MPSOC. The model of the chip is xczu3eg-sfva625-1-i. To implement the interface I use the deserialized LVDS 1:7 in the XAPP585 (https://www.xilinx.com/support/documentation/application_notes/xapp585-lvds-source-synch-serdes-clock-multiplication.pdf)

I have the problem all the time that seems that not all the data lines are well synchronized with the clock itself. I use the cameralink at 85MHz (11.765 ns). I do my simulation of the design with also the TX side to simulate a camera transmitting an image and it goes fine, but when I generate the bitstream seems that the data is not good because we observe a lot of noise in the image and the color of the pixels is not uniform as should be. The fun thing is if I take the patterns of the camera the reception is good.

I am attaching also the code of the 1:7

 

rx_channel_1to7 # (
.LINES (4),
.CLKIN_PERIOD (c_CLK_PER),
.REF_FREQ (c_REF_FREQ),
.USE_PLL ("TRUE"),
.DATA_FORMAT ("PER_CLOCK"),
.CLK_PATTERN (7'b1100011),
.MAX_DELAY (g_MAX_DELAY),
.SIM_DEVICE (g_SIM_DEVICE)
) i_rx (
.clkin_p (clk_p_i),
.clkin_n (clk_n_i),
.datain_p (data_p_i),
.datain_n (data_n_i),
.reset (1'b0),
.idelay_rdy (rdy_i),
.cmt_locked (s_locked),
.px_clk (s_clk),
.px_data (s_px_data),
.px_ready (s_px_rdy)
);

where s_locked and rdy_i are connected to the delayctrl.

And this are the constraints:

create_clock -period 11.765 -name cl_X [get_ports XCLK_P]
set_property CLOCK_DELAY_GROUP ioclockGroup_rx1 [get_nets "design_1_i/design_1_i/CameraLink/cameralink_rx_0/U0/i_x_cl_rx/i_rx/rx_clkdiv*"]

set_false_path -to [get_pins design_1_i/design_1_i/CameraLink/cameralink_rx_0/U0/i_x_cl_rx/i_rx/rxc_gen/iserdes_m/D]
set_false_path -to [get_pins design_1_i/design_1_i/CameraLink/cameralink_rx_0/U0/i_x_cl_rx/i_rx/rxc_gen/iserdes_s/D]
set_false_path -to [get_pins {design_1_i/design_1_i/CameraLink/cameralink_rx_0/U0/i_x_cl_rx/i_rx/rxc_gen/px_reset_sync_reg[*]/PRE}]
set_false_path -to [get_pins {design_1_i/design_1_i/CameraLink/cameralink_rx_0/U0/i_x_cl_rx/i_rx/rxc_gen/px_rx_ready_sync_reg[*]/CLR}]
set_false_path -to [get_pins {design_1_i/design_1_i/CameraLink/cameralink_rx_0/U0/i_x_cl_rx/i_rx/rxc_gen/px_data_reg[*]/D}]
set_false_path -to [get_pins {design_1_i/design_1_i/CameraLink/cameralink_rx_0/U0/i_x_cl_rx/i_rx/rxc_gen/px_rd_last_reg[*]/D}]
set_false_path -to [get_pins {design_1_i/design_1_i/CameraLink/cameralink_rx_0/U0/i_x_cl_rx/i_rx/rxd[*].sipo/px_data_reg[*]/D}]
set_false_path -to [get_pins {design_1_i/design_1_i/CameraLink/cameralink_rx_0/U0/i_x_cl_rx/i_rx/rxd[*].sipo/px_rd_last_reg[*]/D}]

set_property UNAVAILABLE_DURING_CALIBRATION true [get_ports {X_P[3]}]

 

Thank you in advance.

Alen.

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klumsde
Moderator
Moderator
703 Views
Registered: ‎04-18-2011

Maybe take a look at this XAPP which was written for Ultrascale architectures. 

https://www.xilinx.com/support/documentation/application_notes/xapp1315-lvds-source-synch-serdes-clock-multiplication.pdf

In this case it is broadly the same as the 7series one you are mentioning. The IOLOGIC however is different. You need to have a look at thingsl like the reset sequence here. There are considerations around clock skew in the IO column that were not really there in 7-series. 

If the problem is still there you are going to need to look at whats happenning on the data path when it is getting calibrated and the word alignment is getting done at the start. 

 

 

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