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Visitor
Visitor
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Registered: ‎05-08-2018

Can I use DIFF_SSTL18_I or DIFF_HSTL_I_18 or SUB_LVDS for LVDS signals in HR IO bank?

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Hi,

In HR IO bank, only LVDS_25 is supported. But the VCCO is set as 1.8V.

Can I use DIFF_SSTL18_I or DIFF_HSTL_I_18 or SUB_LVDS IO standard?

The LVDS signals contains both input and output.

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-14-2016

Hello,

Yes you can use DIFF_SSTL18_I, DIFF_HSTL_I_18 or SUB_LVDS for implementing your interface.  You do want to confirm that the standard you use will meet the input and output requirements for the device you are interfacing with.  Using the Kintex UltraScale device as an example, you can find this information in DS892, v1.16, Tables 12 and 13.

Thank you,

Sam

 

 

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Xilinx Employee
Xilinx Employee
1,653 Views
Registered: ‎03-14-2016

Hello,

Yes you can use DIFF_SSTL18_I, DIFF_HSTL_I_18 or SUB_LVDS for implementing your interface.  You do want to confirm that the standard you use will meet the input and output requirements for the device you are interfacing with.  Using the Kintex UltraScale device as an example, you can find this information in DS892, v1.16, Tables 12 and 13.

Thank you,

Sam

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-14-2016

You can find the available attributes for each IO Standard in UG571, v1.9 on the tables listed below.

HSTL Class I Allowed Attributes: Table 1-36

SSTL Allowed Attributes: Table 1-44

SUB_LVDS Allowed Attributes: Table 1-69

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