We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Registered: ‎12-17-2018

Clock Gate BUFGCE_1 is not transparent on Amazon F1 instance (xcvu9p-flgb2104-2-i)

I am currenly tring to selectively freeze part of my design running on a F1 instance. I manually instanciated a BUFGCE_1 cell at the root of the module that should be gated. The clock gate ins controlled by memory-mapped i/o that is not part of the gated module. Unfortunately this scheme does not work at all.

To narrow down the possible errors, I created a simple example with only two counters. One has its clock fed through the clock gate, one not. The MSBs of the counters are connected to the vLEDs, the clock gate is controlled by vDIP[0]. The counter connected to the clock gate will never count which gives me the impression that the BUFGCE is intransparent for all settings of vDIP[0]. This small example works when placed 1:1 on an Arty S7-50 board without any issues.

Both designs were run at 15.625 MHz, so the additional delay of the BUFGCE shouldn't hurt the design at all.

What is the correct way of inserting a clock gate, that will result in a working design? The design will operate at maximum 125MHz.

Thanks for yor help.

Tags (3)
0 Kudos