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adam_mira
Observer
Observer
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Registered: ‎01-13-2020

Clock input using regular IO pin (not GC)

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Hi,

Is it possible to use a clock as an input to a  CLB, when that clock arrives from regular IO?

I've been trying to do so, but the tool automatically places a BUFG in the middle and the placement fails.

Adding the CLOCK_DEDICATED_ROUTE constrain set to false, eliminate the BUFG auto-adding but the placement fails again with the error:

Place 30-99 Placer failed with error: 'IO clock placer failed'

Please revise all ERROR, CRITICAL WARNING, and Warning messages

1. Is it even possible to do so in Ultrascale architecture? (I know it is not recommended)

2. If it is possible, what should I do in order to make it work?

3. I searched extensively for a thorough explanation/diagram that layout the path (or possible paths) from pin-to-FF_clock_input without any luck. Is there something you familiar with? (I searched in UG572(UltraScale Architecture Clocking Resources), UG575(UltraScale Device Packaging and Pinouts), UG949(UltraFast Design Methodology Guide), UG574(UltraScale Architecture CLB User Guide))

Thank you!

Adam.

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Accepted Solutions
303 Views
Registered: ‎01-22-2015

@adam_mira 

Is it possible to use a clock as an input to a  CLB, when that clock arrives from regular IO?

As you say ( it is not recommended ) - but, I was able to do it in Vivado v2020.2 and for a xcku5p-ffva676-3.  I used the synthesis option, "-bufg 0" (see page 10 of UG901 v2020.1) to limit the number of BUFG inferred by synthesis.

synth_bufg_0.jpg

As you did, I used the following constraint (as recommended by Vivado) to bring the clock in through a pin that was not a GC-pin.

 

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CLKIN_IBUF_inst/O]

 

Clock constraints like the following are also needed.

 

set_property IOSTANDARD LVCMOS18 [get_ports CLKIN]
set_property PACKAGE_PIN B10 [get_ports CLKIN]
create_clock -period 10.000 [get_ports CLKIN]
set_input_jitter [get_clocks -of_objects [get_ports CLKIN]] 0.1

 


I received a critical warning in synthesis about the CLOCK_DEDICATED_ROUTE constraint, but was able to ignore it.  That is, implementation and bitstream generation ran successfully.

Below is the implementation schematic of my simple test design. You can see that the clock input, CLKIN, has not been routed through a BUFG/BUFGCE.

CLKIN_no_BUFG.jpg

Cheers,
Mark

 

 

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4 Replies
drjohnsmith
Teacher
Teacher
443 Views
Registered: ‎07-09-2009

yes , quiet possible, 

    but not normally done,

 

The Io pins have a much worse delay than the Clock Capable pins,

   leading to very long / great variations

 

Access to the internal fast clock network from a regular IOB is not possible without inheriting an even longer delay .

 

Just make a register, and wire it to an IO pin to check 

what's your language of design ?

 

 

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adam_mira
Observer
Observer
433 Views
Registered: ‎01-13-2020

Thank you,

I am using VHDL. 

I made a register and wired the CLK input to the IO pin and I received the errors I mentioned in the original post.

 

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yannickl
Xilinx Employee
Xilinx Employee
430 Views
Registered: ‎11-03-2016

Hi,

The way I'd go about this is insert your BUFG yourself, use the output of the BUFG for clock, use pre-BUFG as data (which I'd synchronize to whatever clock domain this signal is going to).

If the clock is used to drive an output pin, then keep it as a clock, and use DDR output instead with tied off values.

Regards,

YL

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304 Views
Registered: ‎01-22-2015

@adam_mira 

Is it possible to use a clock as an input to a  CLB, when that clock arrives from regular IO?

As you say ( it is not recommended ) - but, I was able to do it in Vivado v2020.2 and for a xcku5p-ffva676-3.  I used the synthesis option, "-bufg 0" (see page 10 of UG901 v2020.1) to limit the number of BUFG inferred by synthesis.

synth_bufg_0.jpg

As you did, I used the following constraint (as recommended by Vivado) to bring the clock in through a pin that was not a GC-pin.

 

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CLKIN_IBUF_inst/O]

 

Clock constraints like the following are also needed.

 

set_property IOSTANDARD LVCMOS18 [get_ports CLKIN]
set_property PACKAGE_PIN B10 [get_ports CLKIN]
create_clock -period 10.000 [get_ports CLKIN]
set_input_jitter [get_clocks -of_objects [get_ports CLKIN]] 0.1

 


I received a critical warning in synthesis about the CLOCK_DEDICATED_ROUTE constraint, but was able to ignore it.  That is, implementation and bitstream generation ran successfully.

Below is the implementation schematic of my simple test design. You can see that the clock input, CLKIN, has not been routed through a BUFG/BUFGCE.

CLKIN_no_BUFG.jpg

Cheers,
Mark

 

 

View solution in original post