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Participant
Participant
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Registered: ‎05-04-2018

Clock monitor bug

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The Clocking wizard, clock monitor feature does not generate an interrupt vector in xparameters.h file when the interrupt pin is connected to the PL-PS interrupt in an Ultrascale+ device. I think this is a bug. The interrupt pin's property 'TYPE' is set to 'undef' and should probably be set to 'intr'

Does anyone have a workaround for this?

 

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Moderator
Moderator
220 Views
Registered: ‎09-12-2007

Yes, as @sandrao said this is a known issue.

When building the BSP (and the devicetree in Linux too) the tools will use the HSI API to see ports of type interrupt are connected to the interrupt controller.

So, taking a trivial example below:

bd.PNG

Here, I have the clk_wiz interrupt port connected to the Zynq PS irq. However, if we look at the clk_wiz interrupt pin properties:

pin_prop.PNG

This is set to undef. So, when we build the bsp/domain in sdk/vitis and look at the xparameters.h, we will see that the interrupt for this IP is not listed

This is the bug

A workaround:

So, we need to provide a pin with type interrupt. we can do this by creating an interrupt port and looping this to our irq via the HDL wrapper.

To implement this, Right click on the IP Integrator canvas, and select create port:

create_port.PNG

For example:

ext_pin_prop.PNG

Then connect this to your irq:

int_net.PNG

Now, right click on the clk_wiz interrupt pin and make external:

make_ext.PNG

So, now we have two pins, the output clk_wiz/interrupt pin, and the input  clk_wiz_int pin. 

We need to connect this in the HDL wrapper. Here, I have done this in the RTL code:

 

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity top is
end top;

architecture STRUCTURE of top is

signal int_interrupt : STD_LOGIC;

  component design_1_wrapper is
  port (
    clk_wiz_int : in STD_LOGIC;
    interrupt_0 : out STD_LOGIC
  );
  end component design_1_wrapper;
begin
design_1_wrapper_i: component design_1_wrapper
     port map (
      clk_wiz_int => int_interrupt,
      interrupt_0 => int_interrupt
    );
end STRUCTURE;

 

 

 

 

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3 Replies
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Community Manager
Community Manager
270 Views
Registered: ‎08-08-2007

Hi @wadelius 

 

This is a bug and I filed a Change Request against the Clock Mon, thanks for reporting.

Thanks,
Sandy

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Highlighted
Moderator
Moderator
221 Views
Registered: ‎09-12-2007

Yes, as @sandrao said this is a known issue.

When building the BSP (and the devicetree in Linux too) the tools will use the HSI API to see ports of type interrupt are connected to the interrupt controller.

So, taking a trivial example below:

bd.PNG

Here, I have the clk_wiz interrupt port connected to the Zynq PS irq. However, if we look at the clk_wiz interrupt pin properties:

pin_prop.PNG

This is set to undef. So, when we build the bsp/domain in sdk/vitis and look at the xparameters.h, we will see that the interrupt for this IP is not listed

This is the bug

A workaround:

So, we need to provide a pin with type interrupt. we can do this by creating an interrupt port and looping this to our irq via the HDL wrapper.

To implement this, Right click on the IP Integrator canvas, and select create port:

create_port.PNG

For example:

ext_pin_prop.PNG

Then connect this to your irq:

int_net.PNG

Now, right click on the clk_wiz interrupt pin and make external:

make_ext.PNG

So, now we have two pins, the output clk_wiz/interrupt pin, and the input  clk_wiz_int pin. 

We need to connect this in the HDL wrapper. Here, I have done this in the RTL code:

 

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity top is
end top;

architecture STRUCTURE of top is

signal int_interrupt : STD_LOGIC;

  component design_1_wrapper is
  port (
    clk_wiz_int : in STD_LOGIC;
    interrupt_0 : out STD_LOGIC
  );
  end component design_1_wrapper;
begin
design_1_wrapper_i: component design_1_wrapper
     port map (
      clk_wiz_int => int_interrupt,
      interrupt_0 => int_interrupt
    );
end STRUCTURE;

 

 

 

 

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Highlighted
Participant
Participant
180 Views
Registered: ‎05-04-2018

Another workaround with the same effect is to add a VHDL module in the block design with one input signal and one output with property set to intr. Then you dont need to route through the wrapper.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.all;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity type_change_to_interrupt_v1_0 is
port (
in_sig : in std_logic;
out_sig : out std_logic
);
end type_change_to_interrupt_v1_0;

architecture rtl of type_change_to_interrupt_v1_0 is
-- Declare the attributes in the architecture section
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of out_sig : signal is "xilinx.com:signal:interrupt:1.0 out_sig INTERRUPT";
-- Supported parameter: SENSITIVITY { LEVEL_HIGH, LEVEL_LOW, EDGE_RISING, EDGE_FALLING }
-- Normally LEVEL_HIGH is assumed. Use this parameter to force the level
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of out_sig : signal is "SENSITIVITY LEVEL_HIGH";

begin
out_sig <= in_sig;
end rtl;

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