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Visitor kgplotz
Visitor
3,977 Views
Registered: ‎01-09-2017

Clock skew between 2 clock trees driven by different BUFG_GTs

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Hi,

 

An Ultrascale+ design I am working on routes the same incoming 312.5Mhz GTY reference clock to two different BUFG_GTs.  These BUFG_GTs are located next to each other on the die.

 

The first BUFG_GT distributes the same 312.5Mhz clock to roughly 1K flops in a relatively small area.

 

The second BUFG_GT divides the reference clock by 2 and distrubutes a 156.25Mhz clock to roughly 3K flops over a much wider area.

 

There is a small amount of synchronous domain crossing logic that has sources in the 156.25Mhz domain and destinations in the 312.5Mhz domain.

 

These relatively short paths are missing timing mainly due the clock skew between the two synchronous domains. The timing reports show a clock skew of -2.29ns which is approximately 70% of the 3.2ns clock period. The source clock shows a net delay of 2.839ns while the destination clock shows a net delay of 0.576ns.

 

Is anyone aware of any mechanisms provided by the tools or devices to control and minimize the skew between 2 different but synchronous clock domains driven by two different BUFG_GTs?

 

Thanks .. Kevin

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Historian
Historian
6,534 Views
Registered: ‎01-23-2009

Re: Clock skew between 2 clock trees driven by different BUFG_GTs

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You need to inform the placer that these two clocks are supposed to be routed "equally". In UltraScale (as opposed to all previous generations) the clock trees are more dynamic - using the flexible architecture of clock distribution and clock routing channels, the tool can build clock trees that are as big or as small as they need to be.

 

In this case, it is clearly building a smaller domain (with less insertion delay) for the smaller domain, and a larger one (with more insertion delay) for the larger one.

 

The good news is that this is anticipated, and there is an easy fix using the CLOCK_DELAY_GROUP property. This can be set on a bunch of clock nets, and forces the tools to balance the clock insertion of the different clock nets within the group.

 

set_property CLOCK_DELAY_GROUP <name> [get_nets <clk_nets>]

 

Avrum

2 Replies
Highlighted
Historian
Historian
6,535 Views
Registered: ‎01-23-2009

Re: Clock skew between 2 clock trees driven by different BUFG_GTs

Jump to solution

You need to inform the placer that these two clocks are supposed to be routed "equally". In UltraScale (as opposed to all previous generations) the clock trees are more dynamic - using the flexible architecture of clock distribution and clock routing channels, the tool can build clock trees that are as big or as small as they need to be.

 

In this case, it is clearly building a smaller domain (with less insertion delay) for the smaller domain, and a larger one (with more insertion delay) for the larger one.

 

The good news is that this is anticipated, and there is an easy fix using the CLOCK_DELAY_GROUP property. This can be set on a bunch of clock nets, and forces the tools to balance the clock insertion of the different clock nets within the group.

 

set_property CLOCK_DELAY_GROUP <name> [get_nets <clk_nets>]

 

Avrum

Visitor kgplotz
Visitor
3,764 Views
Registered: ‎01-09-2017

Re: Clock skew between 2 clock trees driven by different BUFG_GTs

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Thank you Avrum,

 

That was exactly what I was looking for.

 

Kevin

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