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Visitor
Visitor
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Registered: ‎02-22-2019

Clocking Bad Practice Advisory CLKC-5

Could anybody please advise on this:

The BUFGCE cell i_top_demo/ethipdev_rx_clk_keep_cb[0] i_top_demo/ethipdev_rx_clk_keep_cb[0]/I pin (and CE pin not ACTIVE) is driven by BUFG_GT clock buffer sgmii_clocking/usrclk2_0_bufg_inst. This may be an unnecessary use of multiple clocking resources and should be reviewed. Cascaded buffers introduce skew that can lead to difficult or impossible timing closure.

clkadvisory.PNG

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Xilinx Employee
Xilinx Employee
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Registered: ‎11-03-2016

Hi,

The BUFG(CE) (aka clock buffer) named ethipdev_rx_clk_keep_cb instantiated here in i_ede_top_demo is not needed, you can use the clock from the BUFG_GT (rx_usrclk2) as-is.

Regards,

YL

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Visitor
Visitor
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Registered: ‎02-22-2019

Hi,

Thanks for the response.

This BUFGCE has been automatically inserted by Vivado during synthesis. I think its trying to clockgate. But I am not sure how to remove it.

Is there an attribute to be given ?

If I give an attribute will it ungate and cause hold timing issues?

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