06-17-2020 03:48 AM - edited 06-18-2020 05:05 AM
Could anybody please advise on this:
The BUFGCE cell i_top_demo/ethipdev_rx_clk_keep_cb i_top_demo/ethipdev_rx_clk_keep_cb/I pin (and CE pin not ACTIVE) is driven by BUFG_GT clock buffer sgmii_clocking/usrclk2_0_bufg_inst. This may be an unnecessary use of multiple clocking resources and should be reviewed. Cascaded buffers introduce skew that can lead to difficult or impossible timing closure.
06-17-2020 08:16 AM
The BUFG(CE) (aka clock buffer) named ethipdev_rx_clk_keep_cb instantiated here in i_ede_top_demo is not needed, you can use the clock from the BUFG_GT (rx_usrclk2) as-is.
06-18-2020 01:44 AM
Thanks for the response.
This BUFGCE has been automatically inserted by Vivado during synthesis. I think its trying to clockgate. But I am not sure how to remove it.
Is there an attribute to be given ?
If I give an attribute will it ungate and cause hold timing issues?