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dje666
Explorer
Explorer
2,741 Views
Registered: ‎04-21-2017

Converting Altera Stratix-VGX ALM count the Ultrascale SLC

 Dear Colleagues,

 

I've found data that suggests a basic ALM count can be multiplied by 2.65 to achieve an approximate Logic Cell count. However, the US and US+ architectures now have a System Logic Cell, so what's the ALM to SLC multiplier please?

 

I am looking at a Stratix-5 A7 chip with 234720 ALM's and am trying to determine the best Virtex US or US+ chip to replace it.

 

TTFN,

 

DJE666 

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austin
Scholar
Scholar
2,701 Views
Registered: ‎02-27-2008

d,

 

Far simpler, and accurate, would be to put the verilog or VHDL into Vivado, and run the synthesis step to get a count of resources.

 

Simple quick "rules" are pretty much a waste of time (in my opinion) as every design is different, and the synthesis tool does a lot of work to make efficient use of the resources.  Pick a part with roughly equal CLB to logic block count (or LUT to LUT, DFF to DFF...).

Austin Lesea
Principal Engineer
Xilinx San Jose