Current of LVDS pins driving high during configuration?

[jaharvey]

We have a LVDS output at 2.5v in a KU (XCKU025) device connected to a 1.8v LVDS pins in an ASIC. The common mode and differential specs add up and the functionality is OK.

However, we recently noticed that during power up with the current PUDC configuration, the LVDS P/N gets pulled high to 2.5V for the period during configuration.

The question is, we are trying to find out the amps the Xilinx P/ N pins can source during this time. From the data sheet it looks like it’d be 100uA.

But we are wondering about the impact of both the LVDS P/N pin driving high the LVDS receiver in the ASIC? Would the current still be 100uA?

[markg@prosensing.com]

@jaharvey 

If you connect PUDC_B to GND, then internal pull-up resistors on the SelectIO pins are enabled after power-up and during configuration (UG570 (v1.12), Table 1-9).

Table 3 of the datasheet, DS892, for your device gives values of IRPU which is current associated with the pull-up resistor.  As described in AR#67577, these values of IRPU and the value of VCCO can be used to calculate the effective value of the pull-up resistor.    Knowing the value of the effective pullup resistor can help you with some calculations.

However, as AR#67577 explains, if you are loading the pin with a resistance, REXT, to ground (which maybe describes your ASIC pin), then you can treat max(IRPU) as a constant current source as long as REXT*max(IRPU) < VCCO.

Cheers,
Mark

[jaharvey]

Hi Mark

Thanks for the reply, this is good info.  Thinking about this issue from the other side, if it's reversed with Xilinx being the LVDS receiver. What happens if a 1.8V bank LVDS receiver P/N pins are driven to 2.5V for 2 seconds?

[markg@prosensing.com · Accepted solution]

What happens if a 1.8V bank LVDS receiver P/N pins are driven to 2.5V for 2 seconds?
Most people would simply refer you to the absolute maximum input voltage, Vin, from Table 1 of the datasheet for your device.  For the Kintex UltraScale FPGA, DS892 says that Vin must not exceed VCCO + 0.550.  So, if VCCO=1.8V, then 2.5V exceeds (VCCO +0.550 = 2.35V) and you have exceeded the absolute max input spec for Vin.   If the FPGA is unpowered (ie. VCCO = 0.0V) then things are even worse because 2.5V way exceeds (VCCO+0.550 = 0.550V).

-and, maybe I should leave it at that.

However, I (and probably you) suspect that IO protection for Xilinx FPGAs doesn’t boil down to a simple number for Vin.  Unfortunately, further details are hard to find and are scattered in the Xilinx literature.

For example, Table 2 in DS892 gives a specification for the maximum current, Iin, through a FPGA pin in a power or unpowered bank when forward biasing the clamp diode.  The old figure below for the Virtex-5 shows how the clamp diodes where once wired. 

According to AR#65036, the clamp diodes in UltraScale FPGAs have a forward bias voltage of between 0.43V and 0.64V.  I assume the diodes burnout when current through them exceeds 10mA (ie. the max value Iin from Table 2 of DS892).

So, it looks like current is the killer of FPGA IO and not voltage.  That is, if we can use enough resistance (see RP in Virtex-5 figure) to keep Iin=Ip<10mA then the FPGA IO should not be damaged.   Similarly, if the device sending a digital signal to the FPGA limits output current to <10mA (eg. some LVDS drivers) then the FPGA IO should not be damaged.

So, that’s my interpretation of Xilinx FPGA IO protection.  Use it at your own risk!  

I hope that Xilinx will someday give us a document/blog that clearly explains FPGA IO protection.

Cheers,
Mark

[jaharvey]

Thanks Mark!