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DAC error -Failute at PLL Lock state

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DAC_error.png

 

Hello,

I've been trying to follow the ZCU111 Getting Started Guide https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/57606309/ZCU111+RFSoC+RF+Data+Converter+Evaluation+Tool+Getting+Started+Guide but I'm stuck. When I get to step 13 on the Board Setup, (opening RF_DC_Eval_GUI) the DAC-channels get an error message. "Failure at PLL Lock state" and if I reset it I get

ERROR: Reset EXECUTE
metal: error:      
PLL Lock timeout error in XRFdc_WaitForRestartClr

 

the clock settings are default at 122.88 MHz ref clock and 245.76 MHz at the ADC and DAC channels.

This results in the example programs "rfdc-selftest" etc not working.

What can I do to fix this? Thank you in advance for your help.

mjohansson95
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yes the DACs are stuck in the clock detect state. So we can't program that LMX under any circumstance really. We've tried from the Eval GUI, The System Controller and now from the Zynq PS over I2C. 

I don't know were you purchased the board from but in this case you should try to RMA it if it is in Warranty

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First step is to make sure the RF PLLs were properly programmed. are all 4 LEDs on the edge of the board illuminated?

rfpll_leds.jpg

 

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Hi @klumsde,

No, see the attached picture.
IMG_0028[2].JPG

 

What can I do to fix this?

mjohansson95
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Sorry the 4 LEDs look lit to me

Can you confrim what version of the eval design this is and also what you have on the SD card. 

 

Keith 

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No, the R545 furthest to the right in the picture is not lit, even if it might look like it in the picture.

I run the 2019.2 verision of all software.

On the SD-card I have following files and folders: (according to https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/57770205/RFSoC+RFdc+Build+and+Run+Flow+Tutorial appendix D)

  1. mts folder
  2. nonmts folder
  3. ssr folder
  4. BOOT.bin
  5. image.ub
  6. autostart.sh

 

mjohansson95
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Hi malin.johansson@foi.se 

strange that it is not booting and the DAC clock is not running or not good enough to lock the PLL

Do you look at whats coming out of the UART at the boot time? Anything there to tell you why the clock is not programmed for example. 

Can you try to do one thing. Download the system controller and try to program the RFPLLs from there. 

Use the attached files. 

 

 

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Ah, I think i might have found something in the UART log.
"[19.154705] syncmp_clk_driver_set_rate() set divider failed for pl0_ref_div1, ret = -13"
Does this say something to you?

I downloaded the system controller and put the attached files in the clockFiles, and clicked the "Set LM... Frequency" buttons. But how do I know if the changes were accepted? Nothing was changed anyhow. Still the same error...

mjohansson95
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[ 19.154705] zynqmp_clk_divider_set_rate() set divider failed for pl0_ref_div1, ret = -13

I got it a bit wrong the first time!
mjohansson95
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In the system controller you can go to the window menu and uncheck hide right pane 

Program the PLL again and see what the log is saying 

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No error messages occur when i program the PLL, but it makes no difference in the Evaluation Tool. Still the same error.

This is pretty much what the right pane log says:

PRESSED: Set LMX2594_C Frequency
Starting step sysc

==========

**lots of running sysc func:* ...

SYSC Interpreted Command: [('<resetTIClock:{main iic port}:2F:01>', '', '', ''), ('<writeTIClockFromFile:{main iic port}:2F:01:clockFiles:<1>>', '', '', '')]

SYSC RAW Command: u'IW1\r74\r20\r\tIW1\r2F\rF002\r\tIW1\r2F\r0100259E\r\tIW1\r2F\r0100259C\r\tIW1\r2F\rF002\r\tIW1\r2F\r01700000\r\tIW1\r2F\r016F0000\r\tIW1\r2F\r016E0000\r\tIW1\r2F\r016D0000\r\tIW1\r2F\r016C0000\r\tIW1\r2F\r016B0000\r\tIW1\r2F\r016A0000\r\tIW1\r2F\r01690021\r\tIW1\r2F\r01680000\r\tIW1\r2F\r01670000\r\tIW1\r2F\r01663F80\r\tIW1\r2F\r01650011\r\tIW1\r2F\r01640000\r\tIW1\r2F\r01630000\r\tIW1\r2F\r01620200\r\tIW1\r2F\r01610888\r\tIW1\r2F\r01600000\r\tIW1\r2F\r015F0000\r\tIW1\r2F\r015E0000\r\tIW1\r2F\r015D0000\r\tIW1\r2F\r015C0000\r\tIW1\r2F\r015B0000\r\tIW1\r2F\r015A0000\r\tIW1\r2F\r01590000\r\tIW1\r2F\r01580000\r\tIW1\r2F\r01570000\r\tIW1\r2F\r01560000\r\tIW1\r2F\r0155D300\r\tIW1\r2F\r01540001\r\tIW1\r2F\r01530000\r\tIW1\r2F\r01521E00\r\tIW1\r2F\r01510000\r\tIW1\r2F\r01506666\r\tIW1\r2F\r014F0026\r\tIW1\r2F\r014E0003\r\tIW1\r2F\r014D0000\r\tIW1\r2F\r014C000C\r\tIW1\r2F\r014B09C0\r\tIW1\r2F\r014A0000\r\tIW1\r2F\r0149003F\r\tIW1\r2F\r01480001\r\tIW1\r2F\r01470081\r\tIW1\r2F\r0146C350\r\tIW1\r2F\r01450000\r\tIW1\r2F\r014403E8\r\tIW1\r2F\r01430000\r\tIW1\r2F\r014201F4\r\tIW1\r2F\r01410000\r\tIW1\r2F\r01401388\r\tIW1\r2F\r013F0000\r\tIW1\r2F\r013E0322\r\tIW1\r2F\r013D00A8\r\tIW1\r2F\r013C0000\r\tIW1\r2F\r013B0001\r\tIW1\r2F\r013A8001\r\tIW1\r2F\r01390020\r\tIW1\r2F\r01380000\r\tIW1\r2F\r01370000\r\tIW1\r2F\r01360000\r\tIW1\r2F\r01350000\r\tIW1\r2F\r01340820\r\tIW1\r2F\r01330080\r\tIW1\r2F\r01320000\r\tIW1\r2F\r01314180\r\tIW1\r2F\r01300300\r\tIW1\r2F\r012F0300\r\tIW1\r2F\r012E07FC\r\tIW1\r2F\r012DC0CC\r\tIW1\r2F\r012C0C23\r\tIW1\r2F\r012B0000\r\tIW1\r2F\r012A0000\r\tIW1\r2F\r01290000\r\tIW1\r2F\r01280000\r\tIW1\r2F\r01270001\r\tIW1\r2F\r01260000\r\tIW1\r2F\r01250304\r\tIW1\r2F\r01240040\r\tIW1\r2F\r01230004\r\tIW1\r2F\r01220000\r\tIW1\r2F\r01211E21\r\tIW1\r2F\r01200393\r\tIW1\r2F\r011F43EC\r\tIW1\r2F\r011E318C\r\tIW1\r2F\r011D318C\r\tIW1\r2F\r011C0488\r\tIW1\r2F\r011B0002\r\tIW1\r2F\r011A0DB0\r\tIW1\r2F\r01190624\r\tIW1\r2F\r0118071A\r\tIW1\r2F\r0117007C\r\tIW1\r2F\r01160001\r\tIW1\r2F\r01150401\r\tIW1\r2F\r0114E048\r\tIW1\r2F\r011327B7\r\tIW1\r2F\r01120064\r\tIW1\r2F\r0111012C\r\tIW1\r2F\r01100080\r\tIW1\r2F\r010F064F\r\tIW1\r2F\r010E1E70\r\tIW1\r2F\r010D4000\r\tIW1\r2F\r010C5001\r\tIW1\r2F\r010B0018\r\tIW1\r2F\r010A10D8\r\tIW1\r2F\r01090604\r\tIW1\r2F\r01082000\r\tIW1\r2F\r010740B2\r\tIW1\r2F\r0106C802\r\tIW1\r2F\r010500C8\r\tIW1\r2F\r01040A43\r\tIW1\r2F\r01030642\r\tIW1\r2F\r01020500\r\tIW1\r2F\r01010808\r\tIW1\r2F\r0100249C\r\tIW1\r74\r00\r\t'

SYSC Returned: u'\x08\r:R\r\r:R\r~~~\r:P\rIW1\r74\r20\r:P\r~~~\r:P\rIW1\r2F\rF002\r:P\rIW1\r2F\r0100259E\r:P\rIW1\r2F\r0100259C\r:P\r~~~\r:P\rIW1\r2F\rF002\r:P\rIW1\r2F\r01700000\r:P\rIW1\r2F\r016F0000\r:P\rIW1\r2F\r016E0000\r:P\rIW1\r2F\r016D0000\r:P\rIW1\r2F\r016C0000\r:P\rIW1\r2F\r016B0000\r:P\rIW1\r2F\r016A0000\r:P\rIW1\r2F\r01690021\r:P\rIW1\r2F\r01680000\r:P\rIW1\r2F\r01670000\r:P\rIW1\r2F\r01663F80\r:P\rIW1\r2F\r01650011\r:P\rIW1\r2F\r01640000\r:P\rIW1\r2F\r01630000\r:P\rIW1\r2F\r01620200\r:P\rIW1\r2F\r01610888\r:P\rIW1\r2F\r01600000\r:P\rIW1\r2F\r015F0000\r:P\rIW1\r2F\r015E0000\r:P\rIW1\r2F\r015D0000\r:P\rIW1\r2F\r015C0000\r:P\rIW1\r2F\r015B0000\r:P\rIW1\r2F\r015A0000\r:P\rIW1\r2F\r01590000\r:P\rIW1\r2F\r01580000\r:P\rIW1\r2F\r01570000\r:P\rIW1\r2F\r01560000\r:P\rIW1\r2F\r0155D300\r:P\rIW1\r2F\r01540001\r:P\rIW1\r2F\r01530000\r:P\rIW1\r2F\r01521E00\r:P\rIW1\r2F\r01510000\r:P\rIW1\r2F\r01506666\r:P\rIW1\r2F\r014F0026\r:P\rIW1\r2F\r014E0003\r:P\rIW1\r2F\r014D0000\r:P\rIW1\r2F\r014C000C\r:P\rIW1\r2F\r014B09C0\r:P\rIW1\r2F\r014A0000\r:P\rIW1\r2F\r0149003F\r:P\rIW1\r2F\r01480001\r:P\rIW1\r2F\r01470081\r:P\rIW1\r2F\r0146C350\r:P\rIW1\r2F\r01450000\r:P\rIW1\r2F\r014403E8\r:P\rIW1\r2F\r01430000\r:P\rIW1\r2F\r014201F4\r:P\rIW1\r2F\r01410000\r:P\rIW1\r2F\r01401388\r:P\rIW1\r2F\r013F0000\r:P\rIW1\r2F\r013E0322\r:P\rIW1\r2F\r013D00A8\r:P\rIW1\r2F\r013C0000\r:P\rIW1\r2F\r013B0001\r:P\rIW1\r2F\r013A8001\r:P\rIW1\r2F\r01390020\r:P\rIW1\r2F\r01380000\r:P\rIW1\r2F\r01370000\r:P\rIW1\r2F\r01360000\r:P\rIW1\r2F\r01350000\r:P\rIW1\r2F\r01340820\r:P\rIW1\r2F\r01330080\r:P\rIW1\r2F\r01320000\r:P\rIW1\r2F\r01314180\r:P\rIW1\r2F\r01300300\r:P\rIW1\r2F\r012F0300\r:P\rIW1\r2F\r012E07FC\r:P\rIW1\r2F\r012DC0CC\r:P\rIW1\r2F\r012C0C23\r:P\rIW1\r2F\r012B0000\r:P\rIW1\r2F\r012A0000\r:P\rIW1\r2F\r01290000\r:P\rIW1\r2F\r01280000\r:P\rIW1\r2F\r01270001\r:P\rIW1\r2F\r01260000\r:P\rIW1\r2F\r01250304\r:P\rIW1\r2F\r01240040\r:P\rIW1\r2F\r01230004\r:P\rIW1\r2F\r01220000\r:P\rIW1\r2F\r01211E21\r:P\rIW1\r2F\r01200393\r:P\rIW1\r2F\r011F43EC\r:P\rIW1\r2F\r011E318C\r:P\rIW1\r2F\r011D318C\r:P\rIW1\r2F\r011C0488\r:P\rIW1\r2F\r011B0002\r:P\rIW1\r2F\r011A0DB0\r:P\rIW1\r2F\r01190624\r:P\rIW1\r2F\r0118071A\r:P\rIW1\r2F\r0117007C\r:P\rIW1\r2F\r01160001\r:P\rIW1\r2F\r01150401\r:P\rIW1\r2F\r0114E048\r:P\rIW1\r2F\r011327B7\r:P\rIW1\r2F\r01120064\r:P\rIW1\r2F\r0111012C\r:P\rIW1\r2F\r01100080\r:P\rIW1\r2F\r010F064F\r:P\rIW1\r2F\r010E1E70\r:P\rIW1\r2F\r010D4000\r:P\rIW1\r2F\r010C5001\r:P\rIW1\r2F\r010B0018\r:P\rIW1\r2F\r010A10D8\r:P\rIW1\r2F\r01090604\r:P\rIW1\r2F\r01082000\r:P\rIW1\r2F\r010740B2\r:P\rIW1\r2F\r0106C802\r:P\rIW1\r2F\r010500C8\r:P\rIW1\r2F\r01040A43\r:P\rIW1\r2F\r01030642\r:P\rIW1\r2F\r01020500\r:P\rIW1\r2F\r01010808\r:P\rIW1\r2F\r0100249C\r:P\r~~~\r:P\rIW1\r74\r00\r:P\r~~~\r:P\r~~~\r:P\r'

Finished Set LMX2594_C Frequency
Finished

Could it be something faulty in the  wrapper.bit.bin file on the SD-card? Conisering the error

[   20.347828] fpga_manager fpga0: writing zcu111_rfsoc_trd_wrapper.bit.bin to Xilinx ZynqMP FPGA Manager
[   20.603312] zynqmp_clk_divider_set_rate() set divider failed for pl0_ref_div1, ret = -13

mjohansson95
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I get that message about the clock divider. It isn't anything to worry about. 

 

zcu111_trd_boot.PNG

are you getting it telling you the LMX is programmed?

maybe look at programming the LMX with something else like 491.52Mhz and then doing a shutdown start up of the DAC tile. 

Keith 

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Thank you for continuing helping me.

Yes, my log looks like yours.
I've tried different settings of frequencies and restarting the DAC. Still the same error.

Today I tested to do the BIT test. Not sure if it can be related, bur I got some errors there as well.
See attached log and image.

 BIT-test.png


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Its saying that the tests like IBERT fail. I'd imagine that this needs something on the FMC card to loop back the GTs etc. 

I have never used this. 

Can we check which of DS34, DS35, DS44,DS45 is not lit?

Can you check in the SCUI if all the Power supplies are powered up properly?

 

 

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Hello again,

It's the LED furthest down, so I assume that is DS44 according to the marking in the board?

The VADJ_FMC receives the error attached in the text file.
The voltages are shown in the image below. When I tried to "Set VADJ", nothing changed, but no errors occured in the log.

SCUI_Voltages.png

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And this is the outcome of the Power test

Power.png

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yes. this makes sense because the DAC is not starting and this RF PLL is clocking the DAC. 

try this

shut down the DAC tile 

go to the clocking tab in the RF Eval GUI and try change the PLL to some other frequency. 

See what happens here thenadvanced_clocking.PNG

 

FYI you might need to go into the INI file and add the option to expose advanced clocking

[Display]
ShowExtClock = FALSE
ShowMTS = TRUE
EnableAdvancedClocking = TRUE

 

 

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I still get the error when I press apply.

"ERROR: StartUp EXECUTE
metal: error:    
PLL Lock timeout error in XRFdc_WaitForRestartClr"

Still_error.png

The LED for DS45 also turned black when I applied this step. If I went back to predefined configuration mode of the clocks the DS45 lit up again, but the DS44 remained dark.  

 

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It seems that the issue is with programming that RF PLL and try as we might it never works. 

Can you try out a RF PLL setting that provides the sample clock directly and bypass the internal PLL in the tile. 

If this doesn't work we have to assume the LMX RF PLL3 is damaged. 

 

 

 

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I trired to follow https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/57770205/RFSoC+RFdc+Build+and+Run+Flow+Tutorial Appendix A.1, but i didn't get it to work.

In the attached picture, the DAC PPL are bypassed. Two of the ADC tiles PLL are bypassed and two are not. This indicates that the ADCs are working as they should, but the DACs are still malfunctioning.

part1.png

I'm attaching an image just to show that the PLL's bypassed.

part2.png

How do we continue?

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It seems we can't program this RF pll on the board.

We could try program the device from SDK and see if that works or at least gives us a hint on what is the issue with this device on the i2c/spi bus

If that doesn't work you should contact whoever sold you the kit and look at an RMA, is this a time zero failure? 

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Okey, thanks for all help.

Being a newbie to all this, is it Vitis IDE you mean when you say SDK?

I tried to kind of following this tutorial
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug1209-embedded-design-tutorial.pdf

  • I created a wrapper which is exported to an .xsa file.  
  • I created a platform project
  • I created an application project, and tested both "Hello world" and "peripheral test" which worked just fine.

And are there any example programs using the ADC/DAC that I can look at?
Or which libraries do I need and how do I access the hardware on the zcu111?

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Can I use this guide? https://www.xilinx.com/support/answers/71053.html 

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you can give that a try. I am not confident that it is a SW thing here. 2 seperate applications both fail to program the RF PLL#3 for a variety of settings. 

 

Keith 

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Hi again Keith, 

Now I have ran the xrfdc_read_write_example https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/rfdc/examples/xrfdc_read_write_example.c which returns success. In the xrfdc_selftest_example https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/rfdc/examples/xrfdc_selftest_example.c I only get an error at this part, if I uncomment the return failure the rest of the code returns success. 

	Status = XRFdc_Reset(RFdcInstPtr, XRFDC_DAC_TILE, Tile);
	if (Status != XRFDC_SUCCESS) {
		printf("ERROR16:\n");
		return XRFDC_FAILURE;
	}

Not sure if this says anything else. Is it definitely a faulty LMX RF PLL3?? 

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Can you add in a XRFdc_GetIPStatus into this test beofre and after the reset?

When this gets read you will see where the DAC tiles are in their startup State machine

status = XRFdc_GetIPStatus(RFdcInstPtr, &myIPStatus);
if (status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}

int powerup_status;
int tile_state;
powerup_status = myIPStatus.ADCTileStatus[0].PowerUpState;
tile_state = myIPStatus.ADCTileStatus[0].TileState;

printf("ADC Tile 0 PowerUp Status: %u\n", powerup_status);
printf("ADC Tile 0 State: %u\n", tile_state);

powerup_status = myIPStatus.ADCTileStatus[1].PowerUpState;
tile_state = myIPStatus.ADCTileStatus[1].TileState;

printf("ADC Tile 1 PowerUp Status: %u\n", powerup_status);
printf("ADC Tile 1 State: %u\n", tile_state);

powerup_status = myIPStatus.ADCTileStatus[2].PowerUpState;
tile_state = myIPStatus.ADCTileStatus[2].TileState;

printf("ADC Tile 2 PowerUp Status: %u\n", powerup_status);
printf("ADC Tile 2 State: %u\n", tile_state);

powerup_status = myIPStatus.ADCTileStatus[3].PowerUpState;
tile_state = myIPStatus.ADCTileStatus[3].TileState;

printf("ADC Tile 3 PowerUp Status: %u\n", powerup_status);
printf("ADC Tile 3 State: %u\n", tile_state);

powerup_status = myIPStatus.DACTileStatus[0].PowerUpState;
tile_state = myIPStatus.DACTileStatus[0].TileState;

printf("DAC Tile 0 PowerUp Status: %u\n", powerup_status);
printf("DAC Tile 0 State: %u\n", tile_state);

powerup_status = myIPStatus.DACTileStatus[1].PowerUpState;
tile_state = myIPStatus.DACTileStatus[1].TileState;

printf("DAC Tile 1 PowerUp Status: %u\n", powerup_status);
printf("DAC Tile 1 State: %u\n", tile_state);

 

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Registered: ‎01-07-2020

This is the output I get. State 6, just as in the Evaluation tool...


RFdc Selftest Example Test

Configuring the Clock
LMK04208 configuration write done
LMX configured to frequency 3932160
I2c1 I2CTOSPI LMX2594 PLL configuration done
ADC Tile 0 PowerUp Status: 1
ADC Tile 0 State: 15
ADC Tile 1 PowerUp Status: 1
ADC Tile 1 State: 15
ADC Tile 2 PowerUp Status: 1
ADC Tile 2 State: 15
ADC Tile 3 PowerUp Status: 1
ADC Tile 3 State: 15
DAC Tile 0 PowerUp Status: 0
DAC Tile 0 State: 6
DAC Tile 1 PowerUp Status: 0
DAC Tile 1 State: 6
ERROR16:
ADC Tile 0 PowerUp Status: 1
ADC Tile 0 State: 15
ADC Tile 1 PowerUp Status: 1
ADC Tile 1 State: 15
ADC Tile 2 PowerUp Status: 1
ADC Tile 2 State: 15
ADC Tile 3 PowerUp Status: 1
ADC Tile 3 State: 15
DAC Tile 0 PowerUp Status: 0
DAC Tile 0 State: 6
DAC Tile 1 PowerUp Status: 0
DAC Tile 1 State: 6

mjohansson95
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Registered: ‎04-18-2011

yes the DACs are stuck in the clock detect state. So we can't program that LMX under any circumstance really. We've tried from the Eval GUI, The System Controller and now from the Zynq PS over I2C. 

I don't know were you purchased the board from but in this case you should try to RMA it if it is in Warranty

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Registered: ‎01-07-2020

Thank you for all help. 
I will try to RMA. 

mjohansson95
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Registered: ‎01-24-2020

I got the same timeout error using the rfdc API on ZCU111 boards.

"PLL Lock timeout error in XRFdc_WaitForRestartClr"

My ADCs were fine but my DAC tiles also got stuck in the same state, see prints from my code below:

DAC Tile0 PowerUp State: 0
DAC Tile0 State (end=0x0F): 0x6
DAC Tile0 PLL State: 0
DAC Tile0 Enable: 1

DAC Tile1 PowerUp State: 0
DAC Tile1 State (end=0x0F): 0x6
DAC Tile1 PLL State: 0
DAC Tile1 Enable: 1

 

So I tried testing with one of the Xilinx rfdc driver library examples which I presumed should work.

The "rfdc-selftest" app also returned the same error, when the micro SD card had the contents from the 2019.2 BSP.

When I replaced the contents of the micro SD card with the 2019.1 BSP, and ran "rfdc-selftest", the error went away.

I tried that on two different ZCU111 boards and got the same result.

 

In case you want to try going to 2019.1 BSP image and see if it works.

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Registered: ‎01-07-2020

Thanks for the tip! I'll definitely try that. 

mjohansson95
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