DDR4 bit swap

[trenz-al]

Hi

I can not find any guides on DDR4 bit swap for Xilinx ultrascale devices, for Ultrascale and Ultrascale+ it seems that bit swap withing a byte lane is fully OK as Vivado does not constrain the bits within a lane.

But what about Zynq Ultrascale+ ?

For some reason freescale DDR4 guide says that data lane bitswap for DDR4 is only allowed within a NIBBLE but not within a full bytelane.

For ZU+ I can not find this limitation, so question is if the bit swap withing bytelane is OK or not.

[vsrunga]

@trenz-al

DQ bits with in a byte can be swapped. PG150 mentions this, please refer "Pin Swapping" section page -84 from below link

http://www.xilinx.com/support/documentation/ip_documentation/mig/v1_1/pg150-ultrascale-memory-ip.pdf

You can also try to swap pins with in a byte for any configuration and run rerport_drc in Vivado TCL console and check for violatiins 

Hope this helps

-Vanitha

[vsrunga]

@trenz-al

Above post applies to MIG, but  are you referring PS DDR or MIG?

[trenz-al]

Dear @vsrunga

I asked for Zynq UltraScale+ all the documents you refer talk about Kintex/Virtex Ultrascale and are not relevant in the regard to the PS DDR4 controller on Zynq UltraScale+

So the questions remains: if using x8 or x16 DDR4 components (not DIMM!) on Zynq UltraScale+ PS DDR controller, is byte lane bit swapping within LANE OK or not.

I assume yes, but Xilinx documents to not say it either way.

[vsrunga]

@trenz-al

Yes I realized it a bit late hence posted the second reply.

If this is PSDDR at FPGA end as the pins are dedicated I think swapping concept does not come, you can swap only at memory end, so it would be good to contact the memory vendor and go as per JEDEC spec

I can  inform the concerned team to add this specific information in UG1085

-Vanitha

[trenz-al]

do you know any nibble swap requirements from any DDR4 memory vendor then?

I assume that the nibble restriction in Freescale guide is related to the generic compatibility for x4 and x8 dimms, where you should keep nibbles together to support both x4 and x8 dimms. This would not apply in the case of x8 memory componts that are directly connected to PS DDR. But this is not 100% defined in any available documents, not from Xilinx not from memory vendors.

[vsrunga]

@trenz-al

I think the rule makes sense for X4/X8 chips if they have nibble based DQS but not for other chips with 1:8 DQS_DQ

[trenz-al]

wethinksame then :)

thank you.

[dylan · Accepted solution]

Some PRELIMINARY pin swap rules for the Zynq UltraScale+ PS DRAM controller (not MIG)

LPDDR3/LPDDR4 cannot swap any pins.

DDR3/3L can swap entire byte lanes, and DQ bits around in a byte.

DDR4

For DDR4, if not using the DDR4 write CRC feature, bits in a byte and bytes can be swapped, like DDR3/3L.

If using DDR4 write CRC the following  rules apply:

• Rule 1: Bits within a nibble must stay together
• Rule 2: Nibbles may be swapped within a byte
• (multirank only) Rule 3: Definition of mapping is for rank 0 only. All even ranks have the same DQ mapping as rank 0. Even rank to odd rank mapping is to swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and swap bit 6 with 7

Note- Using a DIMM were the bits may be arbitrary swapped, no swapping can be done as you will not know the ordering without reading the eeprom on the DIMM.

This will be documented in an AR and in ug583 guidelines, please search/check for updated information than this post.

[jawbone_101]

Hello,

Wondering if the "preliminary" solution is official now?

It's been over a year and I do not see an update to UG583 regarding pin swapping rules as it applies to the PS DDR controller, nor do I see an AR. Maybe I missed it.

Thank you

[jawbone_101]

Sorry for the noise.

I found the AR here in case it helps anyone else.

https://www.xilinx.com/support/answers/67330.html

Thanks

[xivtsar]

Hello,

It is still not clear about LPDDR4 pins swapping. I can not find in any Xilinx document mentioned here (AR #67330, UG1075, UG583) complete restriction of pins swapping of LPDDR4. Please, clarify:

1. Please, confirm complete restiction of pins swapping on LPDDR4.

2. Where we can find that in Xilinx documentation? What document. what page, please?

Thanks and best regards,

Igor

[dylan]

See UG1075 v1.7, pg 81:

https://www.xilinx.com/support/documentation/user_guides/ug1075-zynq-ultrascale-pkg-pinout.pdf

[xivtsar]

Dear dylan,

I see on page 81 that DQ bits in bytes 1 and 3 can be swapped. But in your previous message marked as SOLUTION of this topic I see "LPDDR4 cannot swap any pins". So please to be clear answer point by point below with simple YES or NO.

1. Do you confirm the complete restriction of pins swapping you mentioned in your SOLUTION ?

2. If NO, please confirm is DQ bits in bytes 1 and 3 of LPDDR4 PS interface can be swapped on Zynq UltraScale+ devices ?

Thanks,

Igor

[dylan]

Both are valid. I believe Byte 0 and Byte 2 are used to register read operations and so cannot be swapped, and so is a more detailed requirement.

[xivtsar]

Sorry but it still not clear.

It can not be YES both. If no one pin can be swapped (1) then bytes numbers 1 and 3 (2) can not be swapped too.

Please, clarify further.

[dylan]

(1) was cited in 2016 as preliminary. We found that (2) is a more relaxed restriction and supersedes it.