I am using ZCU111. The DAC sampling rate is set to is clocked at 500MSPS. I am using DDS IP to feed a sine wave to DAC and observe on CRO. I want to generate
sine wave of frequency more than 100MHz. In order to check it, I wrote a verilog testbench for the DDS IP. I kept the system clock at 1GHz and output frequency of 200MHz. The following figures show the output waveform and settings of the design.
My questions are -
1. Why am I not getting a Sine wave properly (smooth) in the simulation?
2. Is it possible to generate higher frequencies with DDS IP if sysclk is 1GHz?
3. Is aclk and System clock of DDS IP one and the same? Can they be different? Which one needs to be higher if they are different?
4. From What I understand DDS can generate up to Fs/2 i.e upto 500MHz. If higher frequencies are supported and we feed it to DAC will we be able to see a smooth sine wave or something like a triangular wave (as frequencies increase)?
5. If we want to see a higher frequency signal say at 200MHz, does the sampling rate of RFSoC DAC can stay at 500MSPS or does it need to be higher?