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nmurthy
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Registered: ‎05-27-2018

Decimating Sampling Frequency in RF-ADC of XCZU28DR or XCZU29DR

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I wanted Help in Decimating Sampling frequency of RF-ADC in RFSoC Device.

 

As we know that RF-ADC of RFSOC Device especially XCZU28DR will Support min 1GHz Sampling and XCZU29DR will support min 500MHz input sampling frequency.

One of the RFSOC Design Socket there is situation raised that they wanted to do sampling at 100MHz with input frequency of 70MHz. I would Like to know any way we can achieve this? Can some one provides some idea will be appreciated.

I was thinking to decimate by x8 internally and take it out of RFDC IP and again decimate using FIR or CIC compiler for 100MHz frequency.  Will this approach works? Please also correct me is this understanding correct.

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pthakare
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Registered: ‎08-08-2017

Hi @nmurthy 

Consider for XCZU28DR for which minimum sampling rate is 1GSPS.

You can sample at 1.6 GSPS with x8 decimation . you will get the samples at 200MHz , x2 Decimation in fabric is needed to have samples at 100MHz.

For XCZU29DR

You can sample at 0.8 GSPS with x8 decimation to have samples at 100MHz.

I dont see any issue with this approach .

I would recommend you to use our Frequency planning tool for both the case

https://www.xilinx.com/products/silicon-devices/soc/rfsoc.html#resources

Use the DDC tab in spreadsheet.

 

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pthakare
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Registered: ‎08-08-2017

Hi @nmurthy 

Consider for XCZU28DR for which minimum sampling rate is 1GSPS.

You can sample at 1.6 GSPS with x8 decimation . you will get the samples at 200MHz , x2 Decimation in fabric is needed to have samples at 100MHz.

For XCZU29DR

You can sample at 0.8 GSPS with x8 decimation to have samples at 100MHz.

I dont see any issue with this approach .

I would recommend you to use our Frequency planning tool for both the case

https://www.xilinx.com/products/silicon-devices/soc/rfsoc.html#resources

Use the DDC tab in spreadsheet.

 

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pthakare
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Registered: ‎08-08-2017

Hi @nmurthy 

Adding @vkanchan .

Hi Vivek , we wanted to what is the recommended method to Decimation in fabric , we have options like DDC Compiler, FIR compiler.. for Decimation. 

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klumsde
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Registered: ‎04-18-2011

Hi @nmurthy 

Can you explain why you plan to have the ADC sample rate so low?

You would get better SNR/NSD by making the FS higher in this case. 

You'd need more decimation in the fabric in this case

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