02-16-2016 12:40 AM
According to UG578 and UG579 (GTY and GTH transceivers manuals) there is an information that reference clock inputs should be decoupled by 10 nF capacitors. But looking at VU110 evalution it looks that 100 nF clocks have been used. The only reason is to minimize number of capacitor part types or some technical aspects? 10nF has higher impedance for low frequencies.
02-16-2016 08:16 AM
I suspect that is the case (saving costs).
Generally, if a non-recommended value is chosen, then it is up to you to run the signal integrity analysis to prove it will work.
The are DC block capacitors by the way, NOT decoupling capacitors (the above comment does apply to either), decoupling capacitors are to reduce noise on supplies by providing local fast energy storage.
02-17-2016 04:15 AM
Please follow Xilinx user guides UG578, UG579 recommendations. The user guides recommendations are made based on complete characterization test results.
Evaluation board like VU110 are mainly meant for evaluate/demonstrate FPGA functionality through reference designs and also for training purposes. But they are not meant for PCB/layout design evaluation. (In VU110 board designer might reduce number of decoupling capacitors little bit compare to user guide recommendation (as per his application requirement) to save BOM cost/board space. Please note that Signal Integrity & Power integrity simulations are recommended in that case.)
02-19-2016 12:22 AM
Yes I have used incorrrect naming convention - capacitors are DC blocking not decoupling. Regarding SI simulation currently available IBIS models includes HP and HR banks and LVDS standard. GTY and GTH quads are mostly characterized by IBIS-AMI but if I am correct it includes RX and TX pins. What about REFCLK pins?