Differential Clock input. Cannot set LOC property of ports.

[alexlee256]

 I am trying to connect up a 100MHz management clock from MGTREFCLK pins AH10/AH10 on the FFVB2104, but synthesis gives me the following error relating to location AF11. This is in the same bank, but is not the input that I am attempting to use.

[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance IBUFDS_mgmt_e/DIFFINBUF_INST at AF11 (GTHE3_COMMON_X0Y3) since it belongs to a shape containing instance refclk100_clk_p. The shape requires relative placement between IBUFDS_mgmt_e/DIFFINBUF_INST and refclk100_clk_p that can not be honoured because it would result in an invalid location for refclk100_clk_p. [/path/to/fpga_top.xdc:41]

I have instantiated the following primitives in Verilog:

  // Free-running management clock
  input wire refclk100_clk_n,
  input wire refclk100_clk_p,

....

  wire  mgmt_clk_int;
  wire  mgmt_clk;

  IBUFDS IBUFDS_mgmt_e (
  .O(mgmt_clk_int),
  .I(refclk100_clk_p),
  .IB(refclk100_clk_n)
  );

  BUFG mgmt_buf_2_e(
      .I       ( mgmt_clk_int ),
      .O       ( mgmt_clk )
    );

And my .xdc contains the following lines:

set_property PACKAGE_PIN AH11 [get_ports refclk100_clk_p] // Line 41
set_property PACKAGE_PIN AH10 [get_ports refclk100_clk_n]
set_property IOSTANDARD LVDS [get_ports refclk100_clk_p]
set_property IOSTANDARD LVDS [get_ports refclk100_clk_n]
create_clock -period 10.000 -name mgmt_clk [get_ports refclk100_clk_p]

I have tried omitting the explicit BUFG instantiation but this did not help. Should I be using a different primitive?

I also tried chaining the ODIV2 output of IBUFDS_GTE3 into BUFG_GT as suggested here:
https://forums.xilinx.com/t5/7-Series-FPGAs/UltraScale-error-using-IBUFDS-GTE3-and-BUFG-GT/td-p/490896

However this gave me an even more cryptic error:

"Unable to recover shape constraints after disabling added constraints due to shape constraint generation failure"

What is the correct procedure for bringing up a simple clock input?

Both my attempts seemed equally reasonable to me with refernce to UG578 and UG572.

[austin]

a,

If the pins are for the MGT (transceiver) clock, they may not be used for a generic BUFG connection (nor anything else).

They are dedicated to that use only.

[pratham]

@alexlee256 I dont see you using  IBUFDS_GTE3.

It should work, please check screenshot. I am using 2015.3

[alexlee256]

Hi Austin, Pratham,

Thanks for your replies. I am not actually instantiating the transceivers on that particular bank - I just want to use the clock input. Is it still the case that I must use IBUFDS_GTE3?

My understanding is that the .O() port of UBUFDS_GTE3 can only drive GTYE3_COMMON and GTYE3_CHANNEL. In order to use the clock in the fabric I have to use the .ODIV2() output connected through BUFG_GT. Have I interpreted this correctly? (UG576 Table 2-1).

I have started again from the gtwizard_ultrascale_0_example, and added an additional clock input as below:

This gives the following error message at the start of the implementation run:

 [Vivado 12-1411] Cannot set LOC property of ports, Illegal to place instance IBUFDS_GTE3_MGTREFCLK_CUSTOM_INST on site GTHE3_COMMON_X0Y3. The location site type does not match the instance type. Instance IBUFDS_GTE3_MGTREFCLK_CUSTOM_INST belongs to a shape with reference instance IBUFDS_GTE3_MGTREFCLK_CUSTOM_INST. Shape elements have relative placement respect to each other. The invalid location might results from a constraint on any of the instance in the shape. [/path/to/gtwizard_ultrascale_0_example/gtwizard_ultrascale_0_example.srcs/constrs_1/imports/example_design/gtwizard_ultrascale_0_example_top.xdc:90]

I also tried using the .O() output of IBUFDS_GTE3 without any explicit BUFG_GT instantiation as per your example, but this gave exactly the same error.



Why is Vivado attempting to place the IBUFDS_GTE3 at GTHE3_COMMON_X0Y3? The clock pins I am trying to use are located in GTH Quad 227 which is X1Y12 - X1Y15.

I am also confused as to the nomenclature as X0Y0 is within a GTY transceiver Quad not a GTH. Therefore I would have expected the above to say GTYE3_COMMON_X0Y3?

Thanks,

Alex

[alexlee256]

It seems that this particular error message is generated when both sides of the differential clock input are given pin constraints in the .xdc.

Removing the constraint for the "n" side removes the error message in my case, but I am confused as to how the existing refernce clock pins mgtrefclk0_x0y0_n and mgtrefclk0_x0y0_p are both specified in the example .xdc without giving the same error?

[venkata]

Your understanding about the usage of GT reference clock to fabric is correct. You should be using ODIV2 port for this connectivity.

The error looks to be not expected as per your usage. Could you share a test case to reproduce your observations?

[alexlee256 · Accepted solution]

I had my differential pins connected the wrong way around in my test case, which was causing the error!

(p and n swapped)