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Observer shixiaoke
Observer
246 Views
Registered: ‎07-04-2018

Drive a MMCM and IDELAYE3 with one external lvds clock (at xczu3eg-sbva484-1-e)

In my vivado project , I want to use one external lvds clock as a clock signal to drive a MMCM , and use it as a data signal to transmit to IDELAYE3.

But the vivado prints out  "IO port 'clk_p' is driving multiple buffers. This will lead to unplaceable/unroutable situation."

How can I fix this error ?

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4 Replies
207 Views
Registered: ‎01-22-2015

Re: Drive a MMCM and IDELAYE3 with one external lvds clock (at xczu3eg-sbva484-1-e)

@shixiaoke 

In UltraScale devices, the output of IBUFDS cannot drive both MMCM and IDELAYE3 via dedicated routing.
(14Jan20 Edit): The above statement is wrong - please see correction in 14Jan20 post below.

It is possible to route the IBUFDS output into the FPGA fabric (ie. use non-dedicated routing) and from there into both MMCM and IDELAYE3.DATAIN.  However, this type of routing is not recommended since it can degrade the quality of the clock and make it difficult to pass timing analysis.

However, delaying a clock using IDELAYE3 is often equivalent to phase-shifting a clock with an MMCM. 

That is, for your design, you could route the clock from the IBUFDS output only to the MMCM.  Then, the MMCM can be configured so that one of the clock outputs is a phase-shifted version of the input clock – and this can serve as delayed version of the input clock.  The same MMCM can be configured to produce other clock outputs (with different frequencies and phase shifts) that you can use for other purposes.

Mark

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Guide avrumw
Guide
181 Views
Registered: ‎01-23-2009

Re: Drive a MMCM and IDELAYE3 with one external lvds clock (at xczu3eg-sbva484-1-e)

In UltraScale devices, the output of IBUFDS cannot drive both MMCM and IDELAYE3 via dedicated routing.

I am not convinced this is true...

The IDELAYE3 is inside the IOB, so there is certainly a connection from the IBUFDS to the IDELAYE3.

On a clock capable pin, there is a dedicated connection from the IBUF/IBUFDS to the clocking resources.

I see no reason why these two cannot be used simultaneously.

What you cannot do in UltraScale/UltraScale+/Versal is use the output of the IDELAYE3 as an input to the clocking resources - this was legal in previous families. However, the implementation of the IDELAYE3 is fundamentally different than the IDELAY in the previous generations - the IDELAYE3 is a DLL like device that has too much jitter to be a "good quality" clock. As a result, I suspect that there isn't a dedicated route for connecting the output of the IDELAYE3 to the clocking resources.

But back to the original problem. Most likely the problem is how these components are instantiated. The pin of the FPGA (the top level port of your design) must be connected  to one and only one IBUF/IBUFDS - that is the only physical connection that can be made. From there, it can go multiple places (via dedicated and non-dedicated routes) inside the FPGA.

If the MMCM is built using the Clocking Wizard, then the Wizard puts all the clocking resources into the IP core generated - this includes (optionally) an IBUFDS (and the output clock buffers - BUFGCE/BUFGCE_DIV/BUFGCTRL).

In any circumstance where an input pin of the FPGA (the top level port of the design) is connected to anything other than an IBUF/IBUFDS, the tools will automatically insert an IBUF/IBUFDS (since it has to be there).

So, if you connect both a clocking wizard generated IP core that has an IBUFDS inside it, and an IDELAY directly to to the FPGA pin (top level port), the tools can't make this work. The output of the IBUFDS isn't usable/visible to the rest of the design, so the tools have no choice but to put a second IBUFDS in front of the IDELAYE3. This leaves two IBUFDS in parallel, which is illegal, and generates the message you see.

The solution is to take the IBUFDS out of the clocking wizard core - there is an option for that. On the first pane of the clocking wizard, at the bottom there is a section for "Input Clock Information" - you probably have "Differential clock capable pin" - you need to change it to "No Buffer".

Now, ideally, you should manually insert the IBUFDS into your top level design and then connect the output to both the clock wizard generated core, and to the IDELAYE3 - that is what is really necessary. However, even if you don't manually insert the IBUFDS (and just connect the top level port to both the input of the clock core and the IDELAYE3) the tool should automatically insert the IBUF (or IBUFDS if the pin is using a differential I/O standard).

Avrum

Guide avrumw
Guide
171 Views
Registered: ‎01-23-2009

Re: Drive a MMCM and IDELAYE3 with one external lvds clock (at xczu3eg-sbva484-1-e)

Actually - I just looked at your code - you do not use the clock wizard. But you manually instantiated two parallel IBUFDS - one an IBUFDS and the other an IBUFDS_DIFF_OUT - you can have only one. I suspect that you can just instantiate the IBUFDS_DIFF_OUT, and connect the clkin_p_i to both the IDELAYE3 and the "other stuff" in your design (I haven't use an IBUFDS_DIFF_OUT in UltraScale*).

That being said, your clocking is a bit of a mess. If you are going to go to an MMCM/PLL, you should go directly from the IBUFDS, and not through a BUFG (as you are doing now). You also have lots of BUFG/BUFGCE_DIV in your design - more than one would expect to find. I haven't reverse engineered all the connections, but it looks like the structure is more complex than it should be. Why don't you describe what you need and/or show a schematic of what you have...

Avrum

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79 Views
Registered: ‎01-22-2015

Re: Drive a MMCM and IDELAYE3 with one external lvds clock (at xczu3eg-sbva484-1-e)

@shixiaoke 

Avrum is correct (and I am wrong) – in an UltraScale device, it is possible to simultaneously connect both IDELAY and MMCM to the output of IBUFDS.  As shown below, I was able to do this using Vivado v2018.3 and the XCKU5P.  Note that CLKI1_P and CLKI1_N are a global-clock pin-pair. To prevent Vivado from automatically inserting a BUFGCE between the IBUFDS and the other two components, you may need to use the synthesis option, CLK_BUFFER_TYPE=NONE (ref UG901), and the implementation option, -no_bufg_opt (ref UG904).
IDELAY_and_MMCM.jpg

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