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439 Views
Registered: ‎08-02-2018

Dynamic configuration of clock ip : C_BASE_ADDR

Hi,

 

I am trying to dynamically configure PLL by writing to registers using SPI and the AXI4 Lite interface of clock ip is fed data and address from the registers mentioned above. But I need to know C_BASE_ADDR  to write to the correct address to configure the clock ip. Here the block which converts the SPI data to AXI4 Lite acts as the master for the AXI4 Lite interface of the clock ip.

 

I am currently using Kintex Ultrascale+ (xcku5p)

 

How can I know about C_BASE_ADDR in this case?

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Xilinx Employee
Xilinx Employee
398 Views
Registered: ‎06-02-2017

回复: Dynamic configuration of clock ip : C_BASE_ADDR

Hi a-maheswaranr,

 

You can check the Base address of each module in your block design in the Address Editor.

You can also edit it here.

 

 

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