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ksram1988
Contributor
Contributor
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Registered: ‎07-16-2019

Enabling External Reference Clock Input to Clkin1 (J109) port of ZCU111.

Hi

 

We tried configuring Clkin1 port (J109) as input for providing a reference clock of frequency 10MHz from external reference to the ZCU111 board. For this we have disabled En_Clkin0 and enabled En_CLKin1 in Dual PLL Mode, Int VCO (of LMK04208 in TICS Pro v1.7.2.0) and selected Clkin1 to propagate to PLL1 input through the select MUX. We exported the HEX Register values and configured the clocks through SCGUI. However much to our surprise, we notice Clkin0 continues to propagate with its default frequency of 122.88MHz. This limitation in Dual PLL, Int VCO Mode is preventing us to use PLL1 achieve higher frequencies than the reference clock needed for our design. We are also attaching the Hex Register text files for the below shown two modes.

 

Default.PNGRefCon.PNG

 

However in External VCO Mode, We could observe the reference Clock propagate to the ClkOut5 port (J108) through clock distribution network. Hence we could achieve only those frequencies less than or equal to the reference clock (10MHz) for operating the board.

 

We appreciate if somebody can help us in resolving this issue and help in enabling Clkin1 for referencing the external.

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klumsde
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Registered: ‎04-18-2011

Hi, 

the solution to this is discussed here:

 

https://forums.xilinx.com/t5/Versal-and-UltraScale/Synchronize-external-LO-with-ZCU111/td-p/1043394#M16277

 

Keith

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ksram1988
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Registered: ‎07-16-2019

Hi @klumsde

 

We tried as given in the link https://forums.xilinx.com/t5/Versal-and-UltraScale/Synchronize-external-LO-with-ZCU111/td-p/1043394#M16277 . 

We disabled ClkIn0 and Enabled ClkIn1. We gave a 10MHz external reference. Even when we remove the external reference, we are still be able to observe the clock out of J108, which shows that ClkIn0 is getting fed to PLL1, not ClkIn1. 

Any help on this would be appreciated.

 

Thanks

 

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vaibhav.kardale
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Registered: ‎09-29-2018

Even when you remove the external reference, if you are still be able to observe the clock out of J108 then that clock is not generating from J109, instead it is using on board clocks.

You can try following things in addition to whatever given in Solved: Synchronize external LO with ZCU111 - Community Forums (xilinx.com)

- In LMK04208, change device mode to clock distribution, set the frequency as shown in following screenshots.

- In clock output tab, set the clkout 3 and 4 for your data converter tile input clocks. clkout5 will be your reference output clock at J108.

- You also have to create clock file for LMX2594 which is a RFPLL as shown in attached files.

- Export the register values in .txt format and set the clocks using system controller UI. 

Screenshot (8).png
Screenshot (9).png
Screenshot (10).png
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