FFT IP Core - ZCU102 UltraScale

[fabianolibano]

I have successfully ran the FFT example design provided in this answer record (https://www.xilinx.com/support/answers/58582.html) on the Zynq 7 series.

I am now trying to make it work on the ZCU102 Ultrascale board.

I changed the target part of the project inside of Vivado and then updated the IPs, but one of the ip blocks, called "edge detect" is not available for the ultrascale family, for whatever reason. So, I had to remove it from the block design and attach a constant set to "1" to the "config_tvalid" port of the FFT block.

Whenever I run the application, it hangs at the DMA transfers for some bigger lengths of the FFT. I made sure the set the DMA buffer to the maximum (26 bits).

The weird thing is that, if I take out the run-time configurability of the FFT block, the DMA doesn't get stuck, so I really think it has to do with the deletion of the "edge detect" ip.

Is there a replacement for it? Should the FFT block work with a constant 1 at the "config_tvalid" port? Do you think there is something else that I'm missing in my design?

Thanks.

[bwiec · Accepted solution]

The edge detect is needed because you only want to assert tvalid once to commit a change to the configuration of the FFT. Not surprised it doesn't work with tvalid tied high.

The edge_detect block is just a little custom IP. You could click the 'edit in packager' button and go add the newer devices that have been added to Vivado since that design was posted.

Or a quicker hack i've used before is to tweak the component.xml file. Look for the supportedFamilies tag:

<xilinx:supportedFamilies>
<xilinx:family xilinx:lifeCycle="Beta">artix7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Beta">qzynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Beta">zynquplus</xilinx:family><xilinx:family xilinx:lifeCycle="Beta">azynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Beta">zynq</xilinx:family>
</xilinx:supportedFamilies>

[fabianolibano]

Thanks bwiec,

That worked!