FIFO36E2 FIFO RDCOUNT stuck at zero until RDEN first asserted
I am intstantiating a FIFO36E2 primitive with the parameters shown below in Vivado 2015.4. The state machine surrounding this FIFO needs to wait until a number of words are in the FIFO before beginning, so I am waiting for the output RDCOUNT to pass a certain threshold.
In simulation (using the unisim libraries) I find that once I begin writing data to the FIFO, EMPTY de-asserts after a couple of cycles as expected, and WRCOUNT also begins to increment. However RDCOUNT never increases from zero, so my state machine is stuck.
.CASCADE_ORDER("NONE"), // NONE, FIRST, LAST, MIDDLE, PARALLEL
.CLOCK_DOMAINS("INDEPENDENT"), // INDEPENDENT, COMMON
.EN_ECC_PIPE("FALSE"), // ECC pipeline register, (FALSE, TRUE)
.EN_ECC_READ("FALSE"), // Enable ECC decoder, (FALSE, TRUE)
.EN_ECC_WRITE("FALSE"), // Enable ECC encoder, (FALSE, TRUE)
.FIRST_WORD_FALL_THROUGH("FALSE"), // FALSE, TRUE
.INIT(0), // Initial values on output port
.PROG_EMPTY_THRESH(256), // Programmable Empty Threshold
.PROG_FULL_THRESH(256), // Programmable Full Threshold
// Programmable Inversion Attributes: Specifies the use of the built-in programmable inversion
.IS_RDCLK_INVERTED(0), // Optional inversion for RDCLK
.IS_RDEN_INVERTED(0), // Optional inversion for RDEN
.IS_RSTREG_INVERTED(0), // Optional inversion for RSTREG
.IS_RST_INVERTED(0), // Optional inversion for RST
.IS_WRCLK_INVERTED(0), // Optional inversion for WRCLK
.IS_WREN_INVERTED(0), // Optional inversion for WREN
.RDCOUNT_TYPE("SIMPLE_DATACOUNT"), // RAW_PNTR, EXTENDED_DATACOUNT, SIMPLE_DATACOUNT, SYNC_PNTR
.READ_WIDTH(36), // 4-72
.REGISTER_MODE("UNREGISTERED"), // UNREGISTERED, DO_PIPELINED, REGISTERED
.RSTREG_PRIORITY("RSTREG"), // RSTREG, REGCE
.SLEEP_ASYNC("FALSE"), // FALSE, TRUE
.SRVAL(0), // SET/reset value of the FIFO outputs
.WRCOUNT_TYPE("SIMPLE_DATACOUNT"), // RAW_PNTR, EXTENDED_DATACOUNT, SIMPLE_DATACOUNT, SYNC_PNTR
.WRITE_WIDTH(36) // 4-72
After some experimentation I have found that if I start reading anyway (based on WRCOUNT in simulation), the RDCOUNT output jumps from 0x0 to 0xA, which seems to be a correct conservative estimate (four less than WRCOUNT).
The very strange thing is that RDCOUNT then behaves completely as expected for all subsequent packets - as soon as I start writing to the FIFO is starts to increment again. What could be wrong with the initial state? I am waiting for the RSTBUSY signals to de-assert before writing.
If I set .CLOCK_DOMAINS("COMMON") or .FIRST_WORD_FALL_THROUGH("TRUE") the RDCOUNT output works as expected. ug573-ultrascale-memory-resources states that RDCOUNT is supported in all fifo configurations.
My current workaround is to set .RDCOUNT_TYPE("RAW_PTR") and .WRCOUNT_TYPE("SYNC_PTR") and do a manual subtraction. However this seems inefficient!