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kostas_p
Visitor
Visitor
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Registered: ‎01-21-2016

GTH 16.3 Gb/s Transceivers length on PCB

Hi,

I would like to ask what is the maximum length of a PCB trace that can be routed for a GTH 16.3 Gb/s Transceiver. I have read that the Xilinx FPGAs provide unique auto-adaptive receiver equalization built directly in hard logic.

Is it safer to use a retimer or to use the auto-adaptive receiver equalization which the FPGA supports?

Thank you!


 
 

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austin
Scholar
Scholar
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Registered: ‎02-27-2008

k_p,

 

When you simulate your intended channel, you will see if it works.


As simple as that:  use the simulation models.  Without signal integrity analysis of your layout, with your board's actual construction no one can answer honestly.  The videos clearly demonstrate our superiority and use a standard reference backplane, but your system might not be exactly the same.

 

http://www.xilinx.com/video/fpga/virtex-7-x690t-gth-demo.html

Austin Lesea
Principal Engineer
Xilinx San Jose
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