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david.quinones
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Registered: ‎11-12-2010

GTH voltage rails operating limits

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Hello community

Currently, we are developing a new Kintex UltraScale board. Now I'm working about power and I have some doubts about GTH voltage rails.

Page 320 of UG576 document (Power Up/Down and Reset on Multiple Lanes section talks about current peaks during the changes between power up, power down and reset conditions.and how these peaks can produce issues at the voltage output of power regulators.

The final paragraph of this section says:

In all of these cases, the important consideration is that the voltage at the input pin of the
device must remain within the operating limits as specified in the device data sheets [Ref 6].
Use the Xilinx Power Estimator (XPE) tool to calculate the amount of power required for the
transceivers in your application.
 
My question is about what is referred as "operating limits" in the ds892 data sheet. Is it "Recommended Operating Conditions" or "Absolute Maximum Ratings"?

I suppose that this point has to be verified using simulation of load transient in GTH power circuits.
So, using the worst case maximum current consumption of GTH voltages obtained with Xilinx Power Estimator, the simulation have to apply a rising step from 0A to Max and a falling step from MaxA to 0A and verify if regulator voltage output is between the limits. Could someone confirm this procedure? Remarks are welcome.

"Recommended Operating Conditions" are really tight in order that those voltage peaks meet this requirement, so I suppose that "operating limits" are referred to "Absolute Maximum Ratings". I will really appreciate if someone could verify this point.

I'm looking forward your response.

David Quiñones
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austin
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d.q,

 

For power up/down, absolute limits tell you that the device is damaged at values greater.

 

The recommended limits are for operation.

 

So abs max define the transient limits absolutely on start up or shut down.  After that (before that) values should be in the recommended range.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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austin
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d.q,

 

For power up/down, absolute limits tell you that the device is damaged at values greater.

 

The recommended limits are for operation.

 

So abs max define the transient limits absolutely on start up or shut down.  After that (before that) values should be in the recommended range.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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david.quinones
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Hi Austin

 

So, according to this, I have to use the "Recommended Operating Conditions" limits of ds892 for Vmgtavcc, Vmgtavtt and Vmgtvccaux. That is, +-30mV for MGTAVCC and MGTAVTT and +-50mVpp for MGTVCCAUX. These values are really small!!

 

In the simulations of power regulators is easy to achieve the recommended 10mVpp for steady state. On the other hand, simulations for load transients from 0V to Igthmax show easily higher values than 30mV. What could be good strategies to achieves those margins? Some ideas:

  • Increase Cout, at the output of regulator, until arriving a good result in simulation?
  • Add in the simulation the effect of GTH Power Distribution System? That is, the rising and falling slopes of Igthmax?
  • At the prototype stage verify empirically those margins?

Please, could you confirm these procedures? It would be really useful a formal procedure in the GTH docs to design a good power circuit for this critical part of design.

I will be very grateful with any help about this issue.

 

Best regards

 

David Quiñones

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austin
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d.q,

 

Xilinx has 'power partners' through Avnet.  Their solutions are built and tested.  For example TI, or Maxim solutions rxist (layouts, BOM) for these rails.  Contact them.

 

Yes, the specifications are tight.  They have to be in order to get the performance.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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david.quinones
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Hello Austin

 

As you know, those reference design are general solutions designed to meet the worst case of the biggest reference of the family. I'm in the working phase of create a particular solution from these reference design that meet requirements of voltage accuracy, current, heat and space.

 

Now, please let me do a constructive criticism about the power aspect of Kintex UltraScale. I think is a point poor solved in the documentation.
As programmable logic engineer, 70% of my job is the design with hardware description languages and tools. The other 30% is PCB design. This critical phase takes place at the start of the project, and we try to find an easy solution to power part in order to meet FPGA requirements, in most cases with a expensive solution. The aim in to arrive to the next step of the project as soon as possible to meet the time-to-market.

 

To accomplish this, Xilinx provide to the engineers some user guides with some hundred of sheets. This size of documentation is really inconvenient. The best I have found between all of these sheets is the "GHT Transceiver PCB Design Checklist" of UG576  with the most important tips to take into account, great!. Unfortunately, the only reference about the GTH load transient issue at the end of configuration that must be manage by voltage regulator, is just to verify power supply voltage tolerances in the device data sheet. So, engineers have to decipher the rest of the document trying to find those tiny things that could make that your design don´t work as it must do. This is the case of end of configuration GTH load transient.

 

Excuse me if I'm too much rude. I have invested too much time in this point. My advice is that Xilinx could offer some easy procedures to follow in order to meet requirements, in power, or signal integrity or whatever with references to extended literature. I would be really grateful if Xilinx would work in the user friendly point of her documentation.

 

Thank you for read all this lines.

Best regards.

 

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austin
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David,

 

You are correct (lots of documents, non-trivial, no information on inner workings).

 

Point taken.  I referred your post to management.

 

Sounds like you know the power folks, so all I would say, is to challenge them (price, performance, ease of use).

 

As for load transient, we define abs max as the point at which stresses BEYOND those values may cause damage (some manufacturers define that as where damage occurs -- we do not.  We are fine at those values.)

 

Maximum turn on current is listed in the data sheet, table 7.  Unfortunately Kintex US has no values for the GT supplies.  Not sure why that is.  If the value goes anywhere, it should be there.  I would go with the value of quiescent plus 50 mA (design for an extra 50 mA).  Discuss with your Xilinx sales office to get a FAE to advise (after all, that is what they are there to do).  In addition to our own field engineers, Avnet has just as many, trained by us, to resolve design questions.

Austin Lesea
Principal Engineer
Xilinx San Jose
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david.quinones
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Hello Austin

 

Thank you for your to feedback the complexity of documentation to management. At the end this discussion will bring some positive points.

 

About table 7 of Kintex US datasheet. These values are the MININUM current consumed by FPGA during configuration, and you are right, there is no info about GTH consumption during configuration.

 

The only reference about is in "Power Up/Down and Reset on Multiple Lanes" of UG576 (page 320). In this section refer to the consumption results for GTH rails obtained with XPE. This is for UltraScale devices (UltraScale+ devices excluded), so I suppose the worst case, this is a load transient between 0A to XPE values for GTH voltages.

 

I think the technical case now clear.

Now is time to find a power solution that meet these requirements. I will contact with AVNET to know how many help can they provide.

 

Thank you for your support Austin.

 

Best regards

 

David Quiñones

 

 

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