03-15-2018 12:55 AM
Like the title says I want to generate a clock inside my FPGA whose frequency is slightly offset from my externally provided clock frequency (e.g. 200MHz externally provided and 200.01MHz inside the FPGA). This clock will only be used by few logic elements inside my fpga (just a few flip flops and a simple state-machine).
I have an externally provided clock (let's say 200 MHz) and I need another slightly frequency-shifted clock; frequency shift must be in the 1 ... 10 kHz range so that the resulting clock frequency equals 200.01 MHz. (the absolute value is not too important as long as it's in the aforementioned range. also the value can be fixed).
Since I don't have that frequency avaible externally and I'm not allowed to use external components like PLLs I must generate the clock inside the FPGA. The PLL/MMCM can not provide me with such little frequency shifts (PLEEEEASE TELL ME IF/THAT I'M WRONG WITH THIS ASSUMPTION). If I CAN generate this frequency of 200.01MHz from 200 MHz, please tell me how to do this.I've tried a couple of things but the divider/multiplier values I would need for this can't be selected - or I don't know how (e.g: dividing the 200M down to 10kHz and then Multiplying back to 200.01 MHz)
My idea up to now is to generate a DDS IP core and generate a frequency of let's say 200.0012345.. MHz and just take the sign bit to use it as a clock. Would that be possible or am I overlooking some possible problems here? has anyone done this already?
I'm hoping to get some nice input on my problem ...
Thanks in advance and best regards,
03-26-2018 04:37 AM
Please check the data sheet of the selected device to check the minimum clock out value allowed for MMCM/PLL. I believe 1KHz-10KHz may not be supported.
In that case, you can generate a fabric clock by using simple clock divider logic in RTL and then try to feed it as a clock to selected flops. Please analyze the generated warnings carefully.
03-26-2018 05:05 AM
I'm not looking to generate a slow clock and reading data sheets has actually already crossed my mind.
I'm trying to figure out the most elegant way to generate a AUX-clock out of a different A-clk where AUX-clock's frequency is slightly shifted compared to A-clk. The shift should be in the kHz range. The absolute value should still be in the MHz range. Example: A-clk = 100MHz. AUX-clock = 99.999 MHz
Of course: you would usually go for a PLL. But I don't want to leave the FPGA.The PLL dividers within the FPGA are constrained to a maximum value of 64 (or sth in that range) I guess. For slight frequency shifts you would need a much higher divider/counter values. (Like for my example: 100M / 100000 * 99999 = 99.999 MHz)
03-26-2018 10:49 AM
(PLEEEEASE TELL ME IF/THAT I'M WRONG WITH THIS ASSUMPTION)
You are wrong of course.
Use the dynamic phase shift in the MMCM, and you should be able to bend the 200 MHz output frequency by up to 100 KHz if your VCO frequency is 600 MHz. If the VCO runs at 1200 MHz, the output frequency shift will only be 50 KHz.
Just attach a counter to your 200 MHz output, and then deliver a pulse to the MMCM phase shift enable input once every 12 to 100 clock cycles. Your output frequency will be bent accordingly.
04-03-2018 06:27 AM
@jmccluskwow that trick sounds aweseome I must try that out.
Can you elaborate a little bit more on how I would actually do this?
How did you make up the numbers "every 12 to 100 clock cycles"?
04-03-2018 04:03 PM
The number 12 comes from the documentation on the MMCM.. It takes 12 clock cycles to do a phase shift (minimum). The number 100 is just a number I threw in, and in fact, it has no upper limit how long it can be between phase shifts.