04-20-2019 11:47 AM - edited 04-20-2019 11:55 AM
I'm designing a source synchronous interface between a TI ADS6443 ADC And a Kintex Ultrascale FPGA.
I'll be using a x16 deserialization factor with a 2 wire scheme as descirbed in page 60 - figure 94 of the ADC datasheet:
I want to use the High Speed SelectIO Wizard - but having trouble understanding how exactly to configure it.
For a start:
1. Can someone please explain what's the difference between "Center DDR" and "Center DDR Strobe" in this document (Pages 21 & 22):
Why is one refered to as a "Clock" and the other as a "Strobe" - To me they look absolutely the same...
2. Which one is more appropriate to interface with my specific ADC ?
04-21-2019 02:23 PM
Neither PG188 nor many other Xilinx documents clearly define “strobe”. However, I think the term “strobe” comes from DDR SDRAM memory interfaces where it is sometimes called the DQS line. Like a clock, the strobe edges are used to latch data exchanges that occur in a byte-lane of the memory interface. Unlike a clock, the strobe is not continuous and has different timing for each byte of data (see pg 10 of Xilinx document, WP393), which makes memory interfacing challenging.
For the ADS6443 interface, you should be able to use “Center DDR” and the LVDS clock called DCLKP/M to capture the ADS6443 data.
04-21-2019 03:48 PM
And what should I do with the "Frame Clock" ?
Previously this signal was connected to the CLK_DIV pin of the ISERDES.
I don't see that the component created by the SelectIO Wizard (V3.2) has such a pin.
04-22-2019 07:21 AM - edited 04-22-2019 02:42 PM
I’ve tried reading PG188 about the High Speed SelectIO IP and find that it is very different from the old SelectIO IP that we used with the 7-Series FPGAs. I doubt that I can help you with PG188 any time soon.
However, perhaps you will consider the following alternative to using the High Speed SelectIO IP.
As you know, the old SelectIO IP simply helped us setup the ISERDES primitive. The old SelectIO IP cannot be used with your Kintex UltraScale but this FPGA has the ISERDES3 primitive. You could configure the ISERDES3 yourself (no IP needed) to receive the serialized data from the ADS6443. The method for doing this is nicely described by Fig 2-28 in UG571 and by the the pages surrounding Fig 2-28. This is called Component Mode (as opposed to Native Mode) use of the ISERDES3.
If you are using the ADS6443 ADC at its maximum speed of 80 MSPS, then I think the DDR outputs of the ADS6443 will be running at 320 MHz (640 Mb/s). Since these DDR outputs are byte-streams, you will be setting the ISERDES3 for 1:8 deserialization. Table 23 in DS892 says that Component Mode ISERDES3 can run at rates at/above 1000 Mb/s for DDR 1:8 deserialization, which satisfies the ADS6443 need to run at 640 Mb/s.
04-22-2019 03:07 PM