High Speed SelectIO Wizard 2.0: Designs with multiple banks and phase aligment
I'm new to the UltraScale Architecture and trying to use the High Speed SelectIO Wizard for a receiving stage with 64 differential channels and one clock. In previous threads I could see that the Wizard in version 1.1 was supporting multiple bank designs. My question is how to design a multiple bank receiver core with the current wizard?
The second question is. Do you have a reference design or more documentation about phase aligment in ultrascale? UG571 just documents how to LOAD a specific IDELAY Value or how to increment/decrement the Value. But how to find the eye? Can you recommend or provide a specific algorithm?