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Contributor
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Registered: ‎11-08-2018

HighSpeed SelectIO wizard 3.5 - number of IO high performance IO banks

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Hi!

I have a question on HighSpeed SelectIO wizard and was wondering if anyone can please clarify.

I am using Ultrascale Virtex XCVU080-FFVA2104 device. This device has 15 High Performance I/O banks.

I/O bank - 44, 45, 46, 47, 48, 49, 50, 51, 65, 66, 67, 68, 69, 70 and 71 

I am excluding IO bank 65 as it will have dedicated configuration pins on it.

When I invoke HighSpeed SelectIO wizard, and try to configure the BASIC TAB > Other > Bank section, I only see IO banks 65, 66, 67, 68, 70, 71 available from the drop-down menu. Please see the attached picture.

 

Question 1) Why is the wizard not showing all the 15 High Performance I/O banks ? 

Question 2) Is this IP limitation that I can use HP IO banks - 44, 45, 46, 47, 48, 49, 50 and 51 ?

 

I would like to use all of the 15 available High Performance IO banks.  3 HP for DDR4, 6 HP IO banks for TX at 1600 Mbps and 6 HP IO banks for RX at 1600 Mbps. Which is only possible if the HighSpeed SelectIO wizard can allow the use of HP IO banks 44, 45, 46, 47, 48, 49, 50 and 51.

 

Question 3) Ultrascale Kintex allows the interface speed on HP IO banks to be 1600 Mbps, while Ultrascale Virtex has max data speed of 1400 Mbps , Why is that? Can Ultrascale Virtex support max interface speed of 1600 Mbps?

 

Please advise.

 

HP_banks.jpg
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Moderator
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Registered: ‎08-08-2017

Hi @ami.kum 

This is doable. Let us know if you encountered with any issue while implementing this.

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Moderator
Moderator
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Registered: ‎08-08-2017

Hi @ami.kum 

#1  It should list all  available High Performance (HP) and High Range (HR) banks for the selected device . Seems to be IP bug to me and I will check on this internally . You have not specified the VIVADO version , Can you please once check in latest version (2019.2)?

#2  The workaround can be to select any of the HP bank and modify the location constraints as per not listed bank

#3 , You must be using  Virtex ultrascale in -1 speed grade where maximum data rate supported is 1400 MBPS.

Table 24 , native mode performance specifies this range 

https://www.xilinx.com/support/documentation/data_sheets/ds893-virtex-ultrascale-data-sheet.pdf   

 

Additionally you also mentioned that you are planning to use HSSIO wizard to interface with DDR4 , Why you are not considering to use MIG IP here ?

HSSIO for memory interfacing is not recommended.

 

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Contributor
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Registered: ‎11-08-2018

I am using 2019.2 version.

I was able to clear the issue by starting a new project. When I tried to switch between different devices by using edit settings and changing devices the HSSIO did not update the available banks. Must be something to do with the cache.

 

I will be using MIG for the DDR4 interface.

It is counter intuitive that -1 (fastest) speed grade will have slower interface speed. 

When I picked -2 device I see the data interface speed of 1600 Mbps.

I do have one question. Is there a way to directly assign HSSIO rather than using the GUI? It takes a while to update each pin location and I have 12 of these IO banks which I need to add in I/O planning to generate a pinout. 

 

Thanks. 

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Registered: ‎11-08-2018

Hi! 

I have one follow-up question.

When using HSSIO, do I need to have on differential "Clk Fwd".

When I configure the HSSIO, byte group 2 pin 26 always comes up as "clk"

In my design, I want to use all the byte groups as different TX only. The transmit data is asynhcronous so I don't need to send forward clock out on Byte Group 2 pin 26.

The tool didn't give any error when I has all byte groups as "Data". Just want to confirm if there is any issues with such implementation.

The user guide say CLK FWD needs to less than or equal to DATA. My question is can it be just all DATA ( no CLK FWD).

 

Please clarify.

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Registered: ‎08-08-2017

Hi @ami.kum 

Yes you can have all DATA IOs

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Contributor
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Registered: ‎11-08-2018

Thank you for calrification.

Is there a document which can describes which pin in the I/O bank can be set as RX or TX if I were to have both RX and TX in the same HSSIO I/O bank.

Can I set Byte0 and Byte1 as RX and Byte2 and Byte3 pins as TX.

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Moderator
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Registered: ‎08-08-2017

Hi @ami.kum 

There are certain rules for RX specifically for clock/strobe inputs which are given in Product guide

https://www.xilinx.com/support/documentation/ip_documentation/high_speed_selectio_wiz/v3_5/pg188-high-speed-selectio-wiz.pdf

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Registered: ‎11-08-2018

Hi! 

I did go over the PG188 user guide and notice that I can't combine RX and TX in same nibble while using serial mode.

However, I did not see anything that would prevent me from putting TX on Byte 0 and Byte 1 pins ( differential) and RX on Byte 2 and Byte 3 pins. I believe it should be fine to set up like this. I am using RX in fractional beta mode (asyn).

Just want to confirm with you as I am doing I/O pin planning and don't want to run into issues later on once the pinout is frozen. I am doing pin planning using the HSSIO to validate the pin locations.

Your help would be greatly appreciated if you can let me know that my implementation below is okay and doable. 

I am going to be sharing Bank 71 ( xvcu080 - Virtex Ultrscale - 2 speed grade)  for TX and RX. 

Byte -0 -- TX  (6 diff pair)

Byte - 1 -- TX (3 diff pair)

Byte - 2 --- RX ( 6 diff pair)

Byte - 3 -- RX (3 diff pair)

 

Thanks.

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Moderator
Moderator
343 Views
Registered: ‎08-08-2017

Hi @ami.kum 

This is doable. Let us know if you encountered with any issue while implementing this.

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

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