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niu_zun
Adventurer
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Registered: ‎12-19-2018

How can I use the External DC-Biased circuit for Differential Clock Input?

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Hello ,I have met some questions when I read  the schematic of the eval kit VCU118 with the Vertex Ultrascale+ (XCVU9P).In the schmeatic,Some  CLOCK GENERATORs provide LVDS differential clock for the FPGA. For example,U122(SI5335) provide 125Mhz LVDS for XCVU9P:


 4.png

I obseved that the differerntial clock output is equiped with a  External DC-Biased  circuit :

 5.png

 I can‘t understand why we should use this circuit?In this circuit the VCCO is VCC1V8_FPGA which is 1.8V. In this schematic there are also other External DC-Biased  circuit ,for example:3.png

 

here the VCCO is VCC1V2_FPGA which is 1.2V. I wonder how can I define the VCCO in different DC-based circuits? When shall we adapt the DC-based circuits to our design?

Best wishes and desiring for your answers.

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simon
Xilinx Employee
Xilinx Employee
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Registered: ‎08-25-2010
Hi

No need to place these four resistors if no AC capacitors was connected at the transmitter side. If external termination is used in DC coupling, vicm and vidiff would change, but IBIS simulation is recommend for exact change.
Thanks
Simon
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simon
Xilinx Employee
Xilinx Employee
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Registered: ‎08-25-2010

Hi @niu_zun,

1.8V source should be a typical value(0.9v) to ensure VICM_AC(Input common-mode voltage for AC coupling) is within the range of 0.6V~1.1V, table 15, ds923(V1.9). But it's ok when VICM/VIDIFF/VIN is in the spec, so a lower VICM should be used if VIDIFF is higher.

Thanks
Simon
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niu_zun
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Registered: ‎12-19-2018

hello simon.Thanks for your reply. I still have a question. I observed that the 125MHz LVDS clock from si5335 is not AC-coupling but Dc-coupling.4.png

 5.png

 

 

I wonder whether putting two capciator to adapt the AC-COupling will be better or not. By the way,I don't know why the design integrated the DC-coupling with external DC-based circuit. In my opinion,external DC-based circuit should be used with AC-coupling. If we adapt DC-coupling while the si5335 providing a common voltage of 0.875V,the external DC-based circuit is useless.6.png

 

 

Can you give me some advice? Thank you.

Best wishes and desiring for you reply.

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niu_zun
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Registered: ‎12-19-2018

@simon

hello simon.Thanks for your reply. I still have a question. I observed that the 125MHz LVDS clock from si5335 is not AC-coupling but Dc-coupling.4.png

 

5.png

 



I wonder whether putting two capciator to adapt the AC-COupling will be better or not. By the way,I don't know why the design integrated the DC-coupling with external DC-based circuit. In my opinion,external DC-based circuit should be used with AC-coupling. If we adapt DC-coupling while the si5335 providing a common voltage of 0.875V,the external DC-based circuit is useless.6.png

 

Can you give me some advice? Thank you.

Best wishes and desiring for you reply.

 

 

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simon
Xilinx Employee
Xilinx Employee
719 Views
Registered: ‎08-25-2010
Hi

No need to place these four resistors if no AC capacitors was connected at the transmitter side. If external termination is used in DC coupling, vicm and vidiff would change, but IBIS simulation is recommend for exact change.
Thanks
Simon
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niu_zun
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Registered: ‎12-19-2018
@simon
Hi simon, thanks for your reply. I don't understand why the external termination with DC-coupling can influence the vicm and vidiff of FPGA(XCVU9P)? In my opinion,the vicm and vidff is the solid characteristic of the FPGA. Thank you.
Best wishes and desiring for your reply.
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simon
Xilinx Employee
Xilinx Employee
700 Views
Registered: ‎08-25-2010

Hi @niu_zun,

 

What I said about Vicm/Vidiff means you measured or scoped at the the FPGA side. They both will be affected by the external DC-Biased(not recommended) for DC coupling, but the impact would be limited if the termination resistor is in the k ohm range.

Thanks
Simon
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niu_zun
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Registered: ‎12-19-2018
Thank you @simon.
See you in the next question. hhhhh.
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