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Participant ami.kum
Participant
320 Views
Registered: ‎11-08-2018

How manay ODELAY3 and IDELAY3 primitive are available in Ultrascale XCKU040- 1156 pin package

Can anyone let me know how to find out the max. ODELAY3 and IDELAY3 primitive available in the Ultra scale FPGA.

I tired looking at the Utilization report and it is not clear to me. There are 2 entries BITSLICE_RX_TX (520) and BITSLICE_TX(80) for the XCKU040 Ultrascale.

Also, is it possible to put location constraints on the IDELAY3. I am trying to use IDELAY3 cells for add delay on logic internal to FPGA using the "DATAIN" port on the IDELAY3 preimitive. Would like to control the placement so that these IDELAY3 cell get placed close to the logic.

 

Please advise.

 

AK

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9 Replies
308 Views
Registered: ‎06-21-2017

Re: How manay ODELAY3 and IDELAY3 primitive are available in Ultrascale XCKU040- 1156 pin package

The IDELAY primitive inputs ony connect to input buffers and output buffers respectivley.  You cannot connect the inputs to signals in the FPGA fabric.  Same for the ODELAY outputs.

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Registered: ‎01-22-2015

Re: How manay ODELAY3 and IDELAY3 primitive are available in Ultrascale XCKU040- 1156 pin package

@ami.kum 

     How manay ODELAY3 and IDELAY3 primitive are available in Ultrascale XCKU040- 1156 pin package?

  1. Table 1-1 in UG571(v1.12) says that HP and HR banks support ODELAYE3/IDELAYE3
  2. Table 3-1 in UG571 says that HD banks DO NOT support ODELAYE3/IDELAYE3
  3. The combined number of HP and HR banks in XCKU040FFVA1156 is 10 total (see Fig 1-13 in UG575(v1.12) )
  4. Each I/O bank has 52 pins that can be used for IO (see page-151 of UG571)
  5. Total HP and HR IO is (from 3) and 4)) equal to 520 pins and each has its own BITSLICE_RX_TX that can be configured as either ODELAYE3 or IDELAYE3.

Each ODELAYE3/IDELAYE3 is physically located beside an IO pin.  So, no need for a location (LOC) constraint.

Table 2-11 of UG571 says that DATAIN pin of IDELAYE3 can be “directly driven by the interconnect logic providing a logic accessible delay line”.

bitslice_rx_tx1.jpgbitslice_rx_tx2.jpg

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Participant ami.kum
Participant
255 Views
Registered: ‎11-08-2018

Re: How manay ODELAY3 and IDELAY3 primitive are available in Ultrascale XCKU040- 1156 pin package

DATAIN pin can be connected to internal logic within the FPGA.

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Participant ami.kum
Participant
253 Views
Registered: ‎11-08-2018

Re: How manay ODELAY3 and IDELAY3 primitive are available in Ultrascale XCKU040- 1156 pin package

Thank you for the clarification.

I have couple more question. 

When using IDELAY3, per the UG571 page 175, there is an additional insertion delay added as the signal pass through the multiplexer.

question 1) Is this insertion delay somewhat constant within +/- 25ps across all the IDELAY3 cell on the FPGA or do you think it would be best to calculate it on per IDELAY3 cell basis if the variation is more then +/- 25 ps. 

 

Question 2) What is the  requirement on IDELAYCTRL block. I have multiple IDELAY3 instances. How many IDELAYCTRL are needed if I have say 200 IDELAY3 instances spread across multiple I/O banks. Does the IDELAYCTRL be shared by IDELAY3 on two adjacent I/O banks.

Regards,

AK

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235 Views
Registered: ‎01-22-2015

Re: How manay ODELAY3 and IDELAY3 primitive are available in Ultrascale XCKU040- 1156 pin package

@ami.kum 

     question 1) Is this insertion delay somewhat constant within +/- 25ps across all the IDELAY3 cell on the FPGA or do you think it would be best to calculate it on per IDELAY3 cell basis if the variation is more then +/- 25 ps.

The answer will depend on what you are doing with IDELAYE3.  However, the datasheet, DS922, for your FPGA says below Table 47: “TCAL_ERROR = 24 ps = Calibration error associated with quantization effects based on the IDELAY resolution. Calibration must be performed for each input pin to ensure optimal performance.”

     Question 2) What is the  requirement on IDELAYCTRL block.

UG571(v1.12) says:

  1. Pages 170-171: IDELAYE3 can be used in COUNT mode or TIME mode.  In COUNT mode there is no need to use IDELAYCTRL.  In TIME mode you must use IDELAYCTRL.
  2. Page 194: There is one IDELAYCTRL module per nibble (eight per bank).  
  3. Page 153: A nibble equals a specific group of either 6ea or 7ea BITSLICE_RX_TX.  Each BITSLICE_RX_TX contains both an IDELAYE3 and an ODELAYE3.
  4. Page 194: The IDELAYCTRL module calibrates IDELAYE3 (and ODELAYE3) using the system-supplied REFCLK. The frequency value of this REFCLK is applied to individual IDELAYE3 (and ODELAYE3) primitives with an attribute (REFCLK_FREQUENCY). Each delay element in a nibble therefore requires having this attribute set to the same value.
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Participant ami.kum
Participant
212 Views
Registered: ‎11-08-2018

Re: How manay ODELAY3 and IDELAY3 primitive are available in Ultrascale XCKU040- 1156 pin package

So, if I am using 2 adjacent pins in a I/O bank which are part of same nibble. Can I assume that the same IDELAYCTRL instance be use for both IDELAY3 and ODELAY3. 

Also, How do I let the sythesis tool drive the IDELAYCTRL instance. Is there a XDC constraint. How do know or assign the IDELAYCNTRL instances to various nibble groups.

In my RTL i have 10 instances for IDELAYCNTRL. ( inst0, inst1, .... inst9)


   IDELAYCTRL_inst0 (
      .RDY(rdy),            // 1-bit output: Ready output
      .REFCLK(clk800mhz),   // 1-bit input: Reference clock input
      .RST(calibration_rst)       // 1-bit input: Active high reset input.
      );

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Historian
Historian
205 Views
Registered: ‎01-23-2009

Re: How manay ODELAY3 and IDELAY3 primitive are available in Ultrascale XCKU040- 1156 pin package

Also, How do I let the sythesis tool drive the IDELAYCTRL instance. Is there a XDC constraint. How do know or assign the IDELAYCNTRL instances to various nibble groups.

Take a look at this post on the IDELAYCTRL - While this was written for the 7 series (which have one IDELAYCTRL per bank), the same concepts apply to UltraScale, which have one IDELAYCTRL per nibble.

Avrum

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Participant ami.kum
Participant
193 Views
Registered: ‎11-08-2018

Re: How manay ODELAY3 and IDELAY3 primitive are available in Ultrascale XCKU040- 1156 pin package

In my case, I am not using IDELAY3 from input pin so how can Vivado placement determine which I/O bank to use.

I am using IDELAY3 to add delay to internal signal within the FPGA by connecting the DATAIN port and not IDATAIN port. So, I am not clear on how the IDELAYCTRL gets picked in the I/O bank automatically when there is no information passed to implementation tool. The DATAIN signal is generated as internal logic and routed back to the FPGA.

There must be a way for user to choose which IDELAYCNTRL to use.

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Historian
Historian
183 Views
Registered: ‎01-23-2009

Re: How manay ODELAY3 and IDELAY3 primitive are available in Ultrascale XCKU040- 1156 pin package

Each physical IDELAY is associated with one and only one physical IDELAYCTRL - it is the IDELAYCTRL in the nibble that corresponds to the IOB where the IDELAY lives. Note: I am writing this using the terminology of UltraScale/UltraScale+ - for earlier families (like 7 series) there is one physical IDELAYCTRL per bank instead of per nibble (and all IDELAY/ODELAYs are in an equvalent of TIME mode). 

All IDELAYs are plysically located in the IOBs. When you use an IDELAY for the "normal" use (delaying an input using the IDATAIN input), the IDELAY is implicitly LOCed to the IOB of the pin. When you are using it for an internal data signal, then there is no explicit LOC associated with it; either you assign it with the LOC property, or you let the tool place it (I am not even sure if the tool will automatically place IDELAY elements, or if you need a LOC). But regardless, it will end up in an IOB (since they only exist in IOBs) and each IOB is part of a nibble.

Regardless of how it is placed, the placed IDELAY used will need the physical IDELAYCTRL in the same nibble (if the IDELAY is in TIME mode). All physical IDELAYCTRL are identical (and are implicity connected to the IDELAY/ODELAYs in their nibble), the only thing that differentiates them are the things connected to the ports - the REFCLK and RST coming in and the RDY going out. 

When you write your RTL, you associate each IDELAY in your RTL with an IDELAYCTRL in your RTL. When the IDELAY is placed, the REFCLK, RST and RDY get routed to the physical IDELAYCTRL in the nibble to which that IOB belongs using the signals that are specified in the RTL instantiation of the IDELAYCTRL associated with that IDELAYCTLR RTL instantiation. This means that the tool can replicate a single RTL instance of an IDELAYCTRL into as many nibbles as required in order to have the correct IDELAYCTRL connections for each IDELAYCTRL associated with an IDELAY. Each of these replicated physical IDELAYCTRLs will use the REFCLK, and RST specified in the RTL instantiation of the IDELAYCTRL, and the RDY outputs of all thesereplicated physical IDELAYCTRLs will be OR'ed together and routed to the destination of the RDY output of the RTL instantiated IDELAYCTRL.

The mechanism of associating an RTL IDELAYCTRL with an IDELAY is the IODELAY_GROUP. If you use the same IODELAY_GROUP (which is a string) for an rtl instantiation of an IDELAYCTRL and any number of IDELAY/ODELAYs then these IDELAY/ODELAYs will be associated with that IDELAYCTRL; when the IDELAY/ODELAY is placed, this determines the signals that must be routed to the physical IDELAYCTRL in that nibble. If you do not specify an IODELAY_GROUP in either an RTL instantiated IDELAY/ODELAY or an IDELAYCTRL it belongs to the "default" IODELAY_GROUP (and these will be associated with each other).

This leads to the restrictions on IDELAYs/IDELAYCTRLs:

  • Each RTL instantiated IDELAYCTRL must be in a different IODELAY_GROUP
    • This means only one in the "default" group
    • This can be difficult to manage with IP and wizards that generate interfaces that use IDELAY/ODELAY cells
  • Each IODELAY_GROUP must have an IDELAYCTRL associated with it (unless none of the IDELAY/ODELAY in the group use TIME mode)
  • You cannot have IDELAY/ODELAY in the same nibble that are in different IODELAY_GROUPs
    • The physical IDELAYCTRL in that nibble can have only one set of connections - the one of the RTL instantiation of the IDELAYCTRL with that IODELAY_GROUP

That is the "whole story" with IDELAY/ODELAY and IDELAYCTRLs...

Avrum