How many GC clock should I provide for XCVU9P?

[niu_zun]

Hello,I am making a design with XCVU9P. In the schematic of the eval-kit (VCU118),there are more than one clock provided for GC pin of XCVU9P:

 

I wonder whether only one GC_Clock is neccessary or not. May be the design in the eval kit is made to be more flexible. By the way，I don‘t know the frequecy range of the GC_Clock input. I refered to the ds923 and I wonder if the FREFCLK is the frequecy range of the GC_Clock input.

Thank you.

Best wishes and desiring for your advice.

[drjohnsmith]

It depends what you want to do with th eclock in your design.

Esspecialy when you start out, you need to do a basic FPGA design with th eclocks and resets BEFORE you layout a board.

[niu_zun]

hello 。thanks for your reply.Can you give me some advice about how I can define the design of the GC-clocks including the frequency input range? I don't know which document to refer to .

[drjohnsmith]

Things like clocks, is up to your design, what do you want to do ,

   there is no way we can advize on that ,

As to what frequency range the clock inputs can accept , its in the data sheets,

[niu_zun]

hello @ drjohnsmith

thanks for  your answer. I refer to the datasheet ds923. Can you tell me if the Frefclk in this picture is the range of the GC Clock?

Thank you .

[drjohnsmith]

Nope, thats for the iDelay block of the chip.

where are you connecting the Gclk to in the fpga ?

[niu_zun]

@drjohnsmith hello，Thanks for your reply. I wanna connect the GCLK  to the Pin（ IO_L13P_T2L_N0_GC_QBC
） in the bank 47 as follows:

Which characteristic should I refer to to set the frequency range of GCLK?Thank you .

[drjohnsmith]

Seems your missing the point here,
The pins are multi capable, their speed is set by what you want to do with them, within the limits of what is capable.
The P in FPGA is for programable.
so you need to design your circuit , routing / what you want to do with these pins to know what you want to do with them,

[niu_zun]

I am sorry I  didnt explain what I wanna know clearly. I wanna know what the maximum and the minimum of the GCLK. May be I can refer to the PLL characteristic and MMCM characteristic. 

[gnarahar · Accepted solution]

@niu_zun  GC pins drives the Global buffers (BUFG), MMCM and PLLs in same region. So look at the specs of BUFG, MMCM, PLL in datasheet for Max and Min frequency. No min value available for BUFG though. 

[niu_zun]

@gnarahar  Thank you. Best wishes!