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Observer
Observer
7,715 Views
Registered: ‎10-16-2013

How to control the TX_BITSLICE and RX_BITSLICE of Kintex Ultrascale?

Hi,

 

I am trying to use the RX_BITSLICE and TX_BITSLCE as high speed LVDS interface, But I don't want to use the BITSLICE_CONTROL block,because it will limit the location of IO .

 

My problem is how to control the RX_BIT_CTRL_IN<39:0> and TX_BIT_CTRL_IN<39:0> ports of  RX_BITSLICE and TX_BITSLCE? What does every bit mean?

 

Thank you in advance for your help .

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Xilinx Employee
Xilinx Employee
7,677 Views
Registered: ‎04-16-2012

Hello @4280336 

 

You have to use BITSLICE_CONTROL block for using RX_BITSLICE and TX_BITSLICE components.

TX_BITSLICE/RX_BITSLICE contains output/input delays that can be continuously corrected for VT variation by BITSLICE_CONTROL and serialization logic for either 2:1, 4:1, or 8:1.

 

Thanks,

Vinay

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