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Visitor
Visitor
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Registered: ‎06-12-2017

How to implement 10 bit SERDES in Virtex UltraScale?

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Hi guys,

I need to build 10-bit SERDES from OSERDESE3 but this primitive is not support cascading any more. One solution is to use 10:8 gearbox before OSERDESE3. Is there another way to work around this?

 

Thanks

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-30-2010
10:1 is not natively supported, a gearbox is the solution. We have anew XAPP for 7:1 which can be found here. This could be used as a starting point for a 10:1 design: https://www.xilinx.com/support/documentation/application_notes/xapp1315-lvds-source-synch-serdes-clock-multiplication.pdf
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Xilinx Employee
Xilinx Employee
6,300 Views
Registered: ‎06-30-2010
10:1 is not natively supported, a gearbox is the solution. We have anew XAPP for 7:1 which can be found here. This could be used as a starting point for a 10:1 design: https://www.xilinx.com/support/documentation/application_notes/xapp1315-lvds-source-synch-serdes-clock-multiplication.pdf
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Visitor
Visitor
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Registered: ‎06-12-2017
Thanks. I'm working on gearbox now. I just wonder why you guys remove cascading feature from OSERDESE3. It can save lots of work.
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Community Manager
Community Manager
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Registered: ‎08-08-2007

The Component mode in UltraScale has a reduced feature set than in previous families, no build-in Bitslip, no Cascade, no SDR mode, only supports data widths of 4 and 8. 

What was improved was the Built in Self Calibration BISC to give better tracking across VT. The real improvements are around performance, in memory / native mode the SelectIO support 2.4Gbps DDR4.  

Thanks,
Sandy

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