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yobuwen
Visitor
Visitor
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Registered: ‎05-07-2018

How to implement CameraLink with zynq ultrascale+

CameraLink can be implemented in series-7 FPGA by IP core selectIO.However,how is it implemented in series Ultrascale or Ultrascale+ FPGA‘s. Is there an official alternative IP core?
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sandrao
Community Manager
Community Manager
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Registered: ‎08-08-2007

Hi @yobuwen 

 

There is an Xapp 1315 that covers 1:7 data capture / transmit : https://www.xilinx.com/support/documentation/application_notes/xapp1315-lvds-source-synch-serdes-clock-multiplication.pdf

 

It should work for a CameraLink interface.

 

Sandy

Thanks,

Sandy


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