cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Visitor
Visitor
342 Views
Registered: ‎10-12-2020

I/O Standards rules for Combining with MIPI_DPHY_DCI in the Same Bank

Jump to solution

Hi~ 

I have used a mipi-dphy ip core in vcu118 board, mipi 's I/O standard is MIPI_DPHY_DCI, but how about other IO 's standard should be in the same bank.  Can you list these 'DCI IO standard' which can combining with 'MIPI_DPHY_DCI'.

In PG202, there is: 

Any IO being placed along with D-PHY interface should have DCI IO standard since D-PHY IO uses MIPI_DPHY_DCI IO Standard.

Tags (2)
0 Kudos
Reply
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
301 Views
Registered: ‎03-30-2016

Hello @wgwan 

1. Please read UG571 Chapter 1 "Rules for Combining I/O Standards in the Same Bank" section.
    ( Especially Table 1-77)
2. Before creating a board, please create a simple test design , and run implementation in Vivado to confirm if your IO pin assignment is implementable.

Hope this helps.

Kind regards
Leo

View solution in original post

1 Reply
Xilinx Employee
Xilinx Employee
302 Views
Registered: ‎03-30-2016

Hello @wgwan 

1. Please read UG571 Chapter 1 "Rules for Combining I/O Standards in the Same Bank" section.
    ( Especially Table 1-77)
2. Before creating a board, please create a simple test design , and run implementation in Vivado to confirm if your IO pin assignment is implementable.

Hope this helps.

Kind regards
Leo

View solution in original post