11-09-2020 08:52 AM
I want to drive a CLK104 card from the FPFA CLK104_SFP_REC_CLK_P/N lines. What I/O standard is appropriate for this? I tried LVDS, but that's not a valid option for these pins.
11-09-2020 06:01 PM
From the ZCU208_master.xdc, I find:
set_property PACKAGE_PIN L21 [get_ports "CLK104_SFP_REC_CLK_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_67 set_property IOSTANDARD LVDS [get_ports "CLK104_SFP_REC_CLK_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_67 set_property PACKAGE_PIN M20 [get_ports "CLK104_SFP_REC_CLK_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_67 set_property IOSTANDARD LVDS [get_ports "CLK104_SFP_REC_CLK_P"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_67
Also, from Table 6 in UG1410(v1.0), I find that Bank 67 is an HP bank with VCCO typically set to 1.8V. So, CLK104_SFP_REC_CLK_P and CLK104_SFP_REC_CLK_N on the ZCU208 can receive or send LVDS.
What is telling you that LVDS is not a valid option for these pins?
11-09-2020 06:37 PM
My mistake in the original message. Copy/pasted the wrong content.
The signals I'm interested in are the CLK104_PL_CLK and CLK104_PL_SYSREF coming back from the CLK104 card. These are on pins B7, B8, B9 and B10 (Bank 87). This is also a 1.8V bank, but if I specify LVDS I get errors stating that LVDS is not supported for banks of High Density.
The CLK104_PL_CLK and CLK104_PL_SYSREF are needed for multi-tile synchronization.
11-10-2020 04:56 AM
11-10-2020 10:27 AM
I see what I need to change. I had specified LVDS, when I should have specified LVDS_25.
This seems incorrect to me given that the bank supply is actually 1.8V. But I don't see LVDS_18 as an option.
I now have the following which results in a successful synthesis and implementation:
set_property PACKAGE_PIN B10 [get_ports CLK104_PL_SYSREF_P] set_property PACKAGE_PIN B9 [get_ports CLK104_PL_SYSREF_N] set_property IOSTANDARD LVDS_25 [get_ports CLK104_PL_SYSREF_P] set_property IOSTANDARD LVDS_25 [get_ports CLK104_PL_SYSREF_N] set_property PACKAGE_PIN B8 [get_ports CLK104_PL_CLK_P] set_property PACKAGE_PIN B7 [get_ports CLK104_PL_CLK_N] set_property IOSTANDARD LVDS_25 [get_ports CLK104_PL_CLK_P] set_property IOSTANDARD LVDS_25 [get_ports CLK104_PL_CLK_N] create_clock -period 87.931 [get_ports CLK104_PL_CLK_P] create_clock -period 175.862 [get_ports CLK104_PL_SYSREF_P]