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jimmy.thompson
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Registered: ‎02-19-2016

IBERT Clock Usage

Hi,

I am using an IBERT core on a Virtex Ultrascale part and am having trouble understanding how to use all of the clocks.  The interface I am testing with the IBERT core spans four quads and uses a single reference clock.  However, the IP has several clock inputs (4 bit wide interfaces for gtrefclkx, gtsouthrefclkxx, gtnorthrefclkxx, etc).  

 

I believe that in the top level file where the IBERT is instatiated, the clocks need to be assigned to either 0 or my physical reference clock but I don't understand what the clocks refer to.

 

Can you clarify how the IBERT clocks should be connected and what their use is?

 

Thank you,

Jimmy

 

ibert_clk.jpg

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venkata
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Registered: ‎02-16-2010

As per this option, you only need one GT reference clock driving refclk0 of quad125.
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jimmy.thompson
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Registered: ‎02-19-2016

Thanks for the response.  I understand how to connect the reference clock at the board level but how do you connect the reference clock inputs required by the IBERT core at the top level of my HDL design?  I am referring to clocks shown on the left-side of the image above (gtrefclk, gtnorthrefclk, gtsouthrefclk, etc).  Should those inputs be driven by the quad125 refclk0, driven to 0, or something else?

 

Cheers,

Jimmy

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venkata
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Registered: ‎02-16-2010

The connectivity to those signals are taken care by the IBERT example. Please check it.

You cannot use the IBERT core as part of a HDL design. It needs to be used as a standalone design.
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jimmy.thompson
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Registered: ‎02-19-2016

That is helpful.  Thank you.

 

However, the IBERT example design makes use of the quad125 refclk1 (MGTREFCLK1 125) by connecting it to gty_refclk1_i[1] and gty_qrefclk10_i[1].  In my board design quad125 refclk1 is unused.  Should I still connect this clock as shown in the IBERT example or should something else be done with it?

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venkata
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Registered: ‎02-16-2010

As per the GUI snapshot, the design should have connected MGTREFCLK0 125. Whether you changed the option later?
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jimmy.thompson
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The majority of the clocks in the example design are connected to MGTREFCLK0 125 as I setup in the GUI.  I never changed that or specified MGTREFCLK1 125 at a later point.  However, the two clocks I listed in my above post are connected to MGTREFCLK1 125 and I'm not sure why.  

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venkata
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Registered: ‎02-16-2010

Please provide the .xci file of the IBERT core you have generated.
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jimmy.thompson
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The IBERT core .xci file is attached.  Thanks.

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