02-25-2016 01:00 PM
I am using an IBERT core on a Virtex Ultrascale part and am having trouble understanding how to use all of the clocks. The interface I am testing with the IBERT core spans four quads and uses a single reference clock. However, the IP has several clock inputs (4 bit wide interfaces for gtrefclkx, gtsouthrefclkxx, gtnorthrefclkxx, etc).
I believe that in the top level file where the IBERT is instatiated, the clocks need to be assigned to either 0 or my physical reference clock but I don't understand what the clocks refer to.
Can you clarify how the IBERT clocks should be connected and what their use is?
03-01-2016 09:48 AM
03-01-2016 11:09 AM
Thanks for the response. I understand how to connect the reference clock at the board level but how do you connect the reference clock inputs required by the IBERT core at the top level of my HDL design? I am referring to clocks shown on the left-side of the image above (gtrefclk, gtnorthrefclk, gtsouthrefclk, etc). Should those inputs be driven by the quad125 refclk0, driven to 0, or something else?
03-04-2016 10:03 AM
03-04-2016 10:39 AM
That is helpful. Thank you.
However, the IBERT example design makes use of the quad125 refclk1 (MGTREFCLK1 125) by connecting it to gty_refclk1_i and gty_qrefclk10_i. In my board design quad125 refclk1 is unused. Should I still connect this clock as shown in the IBERT example or should something else be done with it?
03-04-2016 10:50 AM
03-04-2016 10:59 AM
The majority of the clocks in the example design are connected to MGTREFCLK0 125 as I setup in the GUI. I never changed that or specified MGTREFCLK1 125 at a later point. However, the two clocks I listed in my above post are connected to MGTREFCLK1 125 and I'm not sure why.
03-09-2016 09:09 AM